Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A semiconductor structure includes a substrate having a frontside and a backside; a static random-access memory (SRAM) circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells including two inverters cross-coupled together, and a first and second pass gates coupled to the two inverters; a first bit-line disposed on the frontside of the substrate and connected to the first pass gate; and a second bit-line disposed on the backside of the substrate and connected to the second pass gate.

Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, an inductor iron core, and a current transformer trace. The inductor trace is arranged on the primary-side circuit and formed one layer board of the circuit board to serve as a resonant inductor coupled to the primary-side circuit. The inductor iron core includes a core pillar, and the core pillar penetrates a through hole of the circuit board, and the inductor trace surrounds the through hole. The current transformer trace is formed on the circuit board to serve as a current transformer coil coupled to the resonant inductor. The current transformer trace surrounds the through hole to form a common-core structure that shares the inductor iron core.

Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, a primary-side trace, a secondary-side trace, and an iron core assembly. The iron core assembly includes an inductor iron core and an iron core. The primary-side trace surrounds the first through hole in a first direction and surrounds the second through hole in a second direction to form an ?-shaped trace. The inductor trace is formed on the primary-side layer board and coupled to the primary-side trace, and two ends of the inductor trace form an input terminal and an output terminal of the planar magnetic component.

Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.

Abstract: A planar transformer is configured on a multi-layer circuit board of a resonant converter. The planar transformer includes multiple layers of primary-side traces, multiple layers of secondary-side traces, and an iron core. The primary-side traces serve as a primary-side coil of the transformer to generate a first direction magnetic flux when the resonant converter operates. The secondary-side traces serve as a secondary-side coil of the transformer to generate a second direction magnetic flux when the resonant converter operates. The primary-side traces and the secondary-side traces surround a first core pillar and the second core pillar, and the primary-side traces and the secondary-side traces are configured in a specific stacked structure on the multi-layer circuit board, so that a magnetomotive force of the planar transformer can maintain balance during the operation of the resonant converter.

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Abstract: An IC structure includes an SRAM cell. In an embodiment, the SRAM cell includes a channel region over a substrate, a source/drain feature coupled to the channel region, a gate structure intersecting the channel region, and a first contact feature electrically coupled to the source/drain feature and the gate structure. A portion of the first contact feature is disposed directly under the gate structure.

Abstract: A semiconductor device includes multiple transistors formed in a substrate, a frontside power rail disposed on a frontside of the substrate, and a backside power rail disposed on a backside of the substrate. The transistors form at least a first cell functioning under a first power supply voltage and a second cell functioning under a second power supply voltage that is different from the first power supply voltage. The frontside power rail provides the first power supply voltage to the first cell, and the backside power rail provides the second power supply voltage to the second cell.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

Abstract: An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.