Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.

Abstract: A method for determining a consistency coefficient of a power-law cement grout includes: determining a water-cement ratio of the power-law cement grout; according to engineering practice requirements, determining a time required to determine the consistency coefficient of the power-law cement grout; and obtaining the consistency coefficient of the power-law cement grout. The method is accurate and reliable, requires less calculation, etc.; and has very high practical value and popularization value in environmental protection and ecological restoration.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: An electronic device includes a casing, a circuit board and a grounding assembly. The circuit board has a first surface and a second surface, wherein an input terminal and an output terminal are disposed on the second surface. The grounding assembly comprises a conducting terminal, a first grounding element and a second grounding element. The conducting terminal is disposed on the first surface of the circuit board, and the first grounding element is disposed adjacent to the conducting terminal. The first grounding element penetrates the circuit board and electrically couples with the conducting terminal and the casing, and the second grounding element correspondingly penetrates the circuit board and the conducting element, so that a first portion of the second grounding element electrically couples with the input terminal and the output terminal of the circuit board, and a second portion of the second grounding element electrically couples with the conducting terminal.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.

Abstract: A method for determining a three-dimensional tortuosity of a loose and broken rock-soil mass, includes the following steps: a particle grading curve of the loose and broken rock-soil mass is obtained by utilizing a particle size analysis, and followed by calculating an equivalent particle size and an average particle size; a porosity of the loose and broken rock-soil mass is obtained by utilizing a moisture content test, a density test, and a specific gravity test; the three-dimensional tortuosity of the loose and broken rock-soil mass is obtained by utilizing the equivalent particle size, the average particle size and the porosity of the loose and broken rock-soil mass. The method has the advantages of simple logic, accuracy and reliability, simple and fast parameter determination, and has high practical value and promotion value in the field of environmental protection and ecological restoration technology.

Abstract: A crystal oscillator includes an oscillating substrate, a hollow frame, a first electrode, and a second electrode. The oscillating substrate includes a main oscillating region and a thinned region that has a thickness smaller than that of the main oscillating region. The first and second electrodes are disposed on a first surface of the oscillating substrate and a second surface opposite to the first surface, respectively. The hollow frame is disposed on the second surface. The second electrode includes a second electrode portion that has at least one opening in positional correspondence with the thinned region. A method for making the crystal oscillator is also provided herein.

Abstract: A photolithography projection lens, having a plurality of lens elements and a light diaphragm arranged among them, arranged along an optical axis, and comprising an object side and an image side respectively arranged at the front and rear ends of the plurality of lens elements; wherein: the diopters of the two lenses respectively near the object side and the image side must be positive; each of the lens elements is a single lens without cement; the angle between the chief rays at different image height positions and the optical axis is <1 degree, and the angle between the chief rays at different object height positions and the optical axis is <1 degree; and under the projection of 350˜450 nm wavelength light, it provide the imaging effect of precise magnification.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: An automatic target image acquisition and calibration system for application in a defect inspection system is disclosed. During the defect inspection system working normally, the automatic target image acquisition and calibration system is configured to find a recognition structure from an article under inspection, and then determines a relative position and a relative 3D coordinate if the article. Therefore, a robotic arm is controlled to carry a camera to precisely face each of a plurality of inspected surfaces of the article, such that a plurality of article images are acquired by the camera. It is worth explaining that, during the defect inspection of the article, there is no need to modulate an image acquiring height and an image acquiring angle of the camera and an illumination of a light source.