Patents by Inventor Yi Hua
Yi Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11925035Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.Type: GrantFiled: October 26, 2022Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
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Patent number: 11923425Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.Type: GrantFiled: February 17, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen, Chiu-Hua Chung
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240073531Abstract: An automatic target image acquisition and calibration system for application in a defect inspection system is disclosed. During the defect inspection system working normally, the automatic target image acquisition and calibration system is configured to find a recognition structure from an article under inspection, and then determines a relative position and a relative 3D coordinate if the article. Therefore, a robotic arm is controlled to carry a camera to precisely face each of a plurality of inspected surfaces of the article, such that a plurality of article images are acquired by the camera. It is worth explaining that, during the defect inspection of the article, there is no need to modulate an image acquiring height and an image acquiring angle of the camera and an illumination of a light source.Type: ApplicationFiled: August 17, 2023Publication date: February 29, 2024Inventors: FENG-TSO SUN, YI-TING YEH, FENG-YU SUN, JYUN-TANG HUANG, RONG-HUA CHANG, YI-HSIANG TIEN, MENG-TSE SHEN
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 11914432Abstract: A portable electronic device including a first body, a second body, a pivot element, a heat source, a first flexible heat conductive element, and a flip cover is provided. The pivot element is connected to the second body, and the second body is pivotally connected to the first body through the pivot element. The heat source is disposed in the first body. The first flexible heat conductive element is thermally coupled to the heat source and extends toward the pivot element from the heat source. The first flexible heat conductive element passes through the pivot element and extends into the inside of the second body and is thus thermally coupled to the second body. The flip cover is pivotally connected to the first body and located on a moving path of the pivot element.Type: GrantFiled: April 19, 2022Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Chun-Chieh Wang, Wen-Neng Liao, Cheng-Wen Hsieh, Chuan-Hua Wang, Yi-Ta Huang
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Patent number: 11916071Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.Type: GrantFiled: February 23, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok
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Patent number: 11899188Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The first lens group includes a first lens and a second lens, and the second lens group includes a third lens and a fourth lens. One of the third lens and the fourth lens includes one aspheric surface, and each of the lenses in the optical lens system is a singlet lens. The optical lens satisfies a condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm.Type: GrantFiled: August 8, 2022Date of Patent: February 13, 2024Assignee: YOUNG OPTICS INC.Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang
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Patent number: 11899194Abstract: A margin assessment method is provided. Under cooperation of harmonic generation microscopy (HGM) and a deep learning method, the margin assessment method can instantaneously and digitally determine whether a 3D image group generated by an HGM imaging system is a malignant tumor or the surrounding normal skin, so as to assist in determining margins of a lesion.Type: GrantFiled: October 20, 2021Date of Patent: February 13, 2024Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Chi-Kuang Sun, Yi-Hua Liao, Chia-I Chen
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Patent number: 11893300Abstract: A tiled electronic device includes a plurality of display panels, and at least one of the display panels includes a flexible substrate, a pixel, and two signal wires. The flexible substrate has a display portion and a bent portion connected to the display portion. The pixel is disposed on the display portion. The signal wires are disposed on the flexible substrate, and electrically connected to the pixel. Each of the signal wires has a first segment disposed on the display portion, and a second segment disposed on the bent portion. The two first sections have a first pitch, and the two second sections have a second pitch. The first pitch is different than the second pitch.Type: GrantFiled: January 5, 2023Date of Patent: February 6, 2024Assignee: INNOLUX CORPORATIONInventors: Yi-Hua Hsu, Ker-Yih Kao
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Publication number: 20240021639Abstract: A manufacturing method includes the following operations. A lens layer is formed above a substrate. A patterned hard mask layer is formed on the lens layer. The lens layer is etched to transfer a pattern of the patterned hard mask layer to the lens layer such that a plurality of lenses are defined, wherein the lens are micro-lenses or meta-surface lenses. A cladding layer is formed to cover the plurality of lenses and the substrate. Portions of the cladding layer are etched to form a first inclined sidewall and a second inclined sidewall, wherein the first inclined sidewall is above the second inclined sidewall, wherein a projection of the first inclined sidewall on the substrate is spaced apart from a projection of the second inclined sidewall on the substrate.Type: ApplicationFiled: May 17, 2023Publication date: January 18, 2024Inventors: Yi-Hua CHIU, Wei-Ko WANG, Shih-Liang KU
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Publication number: 20230421271Abstract: A transmitter includes a transmitter circuit, a calibration circuit, and a transmitter signal strength indicator circuit. The transmitter circuit is coupled to a power node to receive a supply voltage and transmits an output signal via an antenna. The calibration circuit senses a current of the power node when the transmitter circuit operates in a first frequency band and operates in a second frequency band to generate a signal having different values and generates a calibration signal according to the signals having the different values. The transmitter signal strength indicator circuit detects power of the output signal to generate a first detection signal, and generate a second detection signal according to the calibration signal and the first detection signal. The transmitter circuit adjusts the power of the output signal to be target power according to the second detection signal.Type: ApplicationFiled: June 1, 2023Publication date: December 28, 2023Inventors: CHIA-WEI HUANG, YI-HUA LU
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Publication number: 20230409270Abstract: A tiled electronic device includes a plurality of display panels, and at least one of the display panels includes a flexible substrate, a pixel, and two signal wires. The flexible substrate has a display portion and a bent portion connected to the display portion. The pixel is disposed on the display portion. The signal wires are disposed on the flexible substrate, and electrically connected to the pixel. Each of the signal wires has a first segment disposed on the display portion, and a second segment disposed on the bent portion. The two first sections have a first pitch, and the two second sections have a second pitch. The first pitch is different than the second pitch.Type: ApplicationFiled: August 31, 2023Publication date: December 21, 2023Inventors: Yi-Hua HSU, Ker-Yih KAO
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Publication number: 20230386399Abstract: An electronic apparatus includes a first light emitting array and a second light emitting array. The first light emitting array includes first light-emitting units disposed in a first region and a first sub region. The second light emitting array is disposed adjacent to the first light emitting array. The second light emitting array includes second light-emitting units disposed in a second region and a second sub region. The difference between the average brightness in the first region and the average brightness in the second region is in a range from 0% to 20%, and the difference between the average brightness in the first sub region and the average brightness in the second sub region is less than the difference between the average brightness in the first region and the average brightness in the second region.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Chi-Liang CHANG, Yi-Hua HSU
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Publication number: 20230380072Abstract: A manufacturing method of tape includes the steps of providing a tape including substrate units, providing a die device and a cutting and/or pressing process. Each of the substrate units includes a carrier, a circuit layer, an adhesive and a heat spreader, the heat spreader is attached onto the carrier by the adhesive. In the cutting and/or pressing process, the die device is provided to press the tape to generate separation protrusions on the heat spreader and allow the separation protrusions to protrude from a heat dissipation surface of the heat spreader. When rolling the tape, the separation protrusions can separate the stacked substrate units to prevent the adhesive from being squeezed out to contaminate the tape.Type: ApplicationFiled: February 14, 2023Publication date: November 23, 2023Inventors: Yi-Hui Chen, Yi-Hua Huang, Yen-Ping Huang, Shih-Chieh Chang
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Patent number: 11823821Abstract: The present invention relates to a polymer voltage-dependent resistor (PVDR) in various physical forms and methods for manufacturing the varistor. The body of the PVDR is composed of a polymer matrix having a filler composed of doped zinc oxide particles, other semi conductive particles or metal particles uniformly distributed therein. Conductive electrodes may be affixed to the polymer matrix and electrical leads attached to the electrodes.Type: GrantFiled: November 15, 2022Date of Patent: November 21, 2023Assignee: Dongguan Littelfuse Electronics Company LimitedInventors: Chun-Kwan Tsang, Jianhua Chen, Yi-Hua Deng
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Publication number: 20230369555Abstract: An electronic device includes a substrate, a trace layer and a plurality of electronic components. The substrate defines a thickness less than or equal to 100 µm. The substrate further defines a plurality of transmittances, and at least one of the transmittances is greater than 20% under the condition of the wavelength of light being between 500 nm and 1300 nm. The trace layer is arranged on the substrate, and the trace layer includes a plurality of connection pads. The electronic components are arranged on the substrate. Each electronic component is provided with at least one electrode, which is arranged on a face of the electronic component facing the substrate. At least one electrode of each electronic component is eutectic bonded to one of the connection pads.Type: ApplicationFiled: May 12, 2023Publication date: November 16, 2023Inventors: Yi-Hua WU, Chin-Tang LI
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Publication number: 20230348738Abstract: An example of a liquid ink includes a pigment dispersion, a polyurethane dispersion, a polytetrafluoroethylene wax emulsion, a co-solvent, and a balance of water. A particle diameter of a polytetrafluoroethylene wax in the polytetrafluoroethylene wax emulsion is less than 50 nm. Examples of the liquid ink may be incorporated into a thermal inkjet printing system.Type: ApplicationFiled: July 9, 2023Publication date: November 2, 2023Inventors: Max Yen, Alex Trubnikov, Shimrit Rubin, Or Pinkesfeld, Marisa Samoshin, Yi-Hua Tsao, Eytan Cohen
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Patent number: 11803330Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.Type: GrantFiled: October 27, 2021Date of Patent: October 31, 2023Assignee: SILICON MOTION, INC.Inventors: Jieh-Hsin Chien, Yi-Hua Pao
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Publication number: 20230292149Abstract: A UE performs up to a threshold number of attempts to transmit a default capability message to a base station, the default capability message representing a default set of CA combinations supported by the UE. If transmission is unsuccessful, the UE switches to a compact capability mode in which the UE attempts to transmit compacted UE capability messages representing successively smaller subsets of the default set of CA combinations until either a capability message is successfully received by the base station or a second threshold number of unsuccessful transmission attempts is performed. To facilitate configuration of an initial compacted capability message, the UE maintains a PC list that lists one or more cells that have been identified previously as incapable of receiving default-sized capability messages and that further identifies a representation of a limited subset of CA combinations to include in capability messages sent to a corresponding listed cell.Type: ApplicationFiled: August 6, 2020Publication date: September 14, 2023Inventors: Meng-Hau Wu, Xu Ou, Yu-Cheng Chen, Rukun Mao, Zong Syun Lin, Qin Zhang, Yi-Hua Li