Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack, and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure. The etch stop layer is in contact with the sealing structure.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The insulating wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

Abstract: The present disclosure provides a track transmission system and the track transmission device thereof. The track transmission system comprises at least a track transmission device, a connecting device, and a control device. The track transmission device is provided for disposing slidably at least an electronic device. In addition, signal transmission with the control device can be accomplished through the connecting device. The electronic device is coupled to the circuit board of the track transmission device by contacting. As the electronic device slides along the track transmission device, signal transmission with the control device still can be maintained.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.

Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

Abstract: A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.

Abstract: The present disclosure relates to a track structure capable of supplying power, which comprises a track module, a first conducting module, a second conducting module, at least a sliding module, a first electrical transmission module, and a second electrical transmission module. Each track module is provided for disposing an electronic device. The electronic device slides along the track module via the sliding module. The first electrical transmission module is connected to the electronic device, and a first electrode and a second electrode of the sliding module. The first and second electrodes contact the first and second conducting modules, respectively. The second electrical transmission module is connected to the first and second conducing modules and connected to a power supply. The power supply supplies power and transmit the power to the electronic device through the track structure.

Abstract: The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost.

Abstract: A keyboard-video-mouse (KVM) switch and an operating method thereof are disclosed. The KVM switch is coupled between at least one peripheral device and controlled computers. The method includes steps of: determining whether the hot-key mode of KVM switch is started; if yes, when the KVM switch receives a first signal from a specific controlled computer of the controlled computers, directly passing the first signal to a corresponding specific peripheral device of the at least one peripheral device; when the KVM switch receives a second signal in response from the specific peripheral device within a predetermined period of time, determining whether the second signal includes a specific data; if yes, replacing the specific data in the second signal with an irrelevant data to form a third signal and transmitting the third signal to the specific controlled computer. The irrelevant data corresponds to the specific controlled computer and has no effect on the specific controlled computer.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

Abstract: Novel use of small molecules, particularly indolyl and indolinyl hydroxamates is disclosed herein. The indolyl and indolinyl hydroxamates are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating a patient suffering from heart failure or neuronal injury.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack , and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure . The etch stop layer is in contact with the sealing structure.

Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

Abstract: Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed.

Abstract: A halogen-free resin composition includes (A) 100 parts by weight of epoxy resin; (B) 10 to 100 parts by weight of styrene-maleic anhydride (SMA) copolymer; and (C) 5 to 50 parts by weight of bisphenol S. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby achieve a high glass transition temperature, high heat resistance, and attractive appearance, and thus is suitable for producing a prepreg or resin film to thereby be applicable to copper clad laminates and printed circuit boards.

Abstract: Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: A halogen-free resin composition includes (A) 100 parts by weight of naphthalene epoxy resin; (B) 10 to 100 parts by weight of styrene maleic anhydride copolymer; and (C) 30 to 70 parts by weight of DOPO-containing bisphenol F novolac resin. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby attain a low dielectric constant, a low dielectric dissipation factor, high heat resistance, and high flame retardation, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.