Abstract: Novel use of small molecules, particularly indolyl and indolinyl hydroxamates is disclosed herein. The indolyl and indolinyl hydroxamates are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating a patient suffering from heart failure or neuronal injury.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack , and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure . The etch stop layer is in contact with the sealing structure.

Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

Abstract: Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed.

Abstract: A halogen-free resin composition includes (A) 100 parts by weight of epoxy resin; (B) 10 to 100 parts by weight of styrene-maleic anhydride (SMA) copolymer; and (C) 5 to 50 parts by weight of bisphenol S. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby achieve a high glass transition temperature, high heat resistance, and attractive appearance, and thus is suitable for producing a prepreg or resin film to thereby be applicable to copper clad laminates and printed circuit boards.

Abstract: Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: A halogen-free resin composition includes (A) 100 parts by weight of naphthalene epoxy resin; (B) 10 to 100 parts by weight of styrene maleic anhydride copolymer; and (C) 30 to 70 parts by weight of DOPO-containing bisphenol F novolac resin. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby attain a low dielectric constant, a low dielectric dissipation factor, high heat resistance, and high flame retardation, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.

Abstract: A solid state drive includes a flash memory, a cache memory, and a controlling unit. The solid state drive is in communication with a host. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The cache memory includes a plurality of cache units. The cache units are allocated into a plurality of groups according to operating statuses of respective cache units. The controlling unit is in communication with the host, the flash memory and the cache memory. Under control of the controlling unit, a write data from the host is temporarily stored in the cache memory so as to be written into the flash memory, or a read data from the flash memory is temporarily stored in the cache memory so as to be provided to the host.

Abstract: Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed.

Abstract: A data transmission control method for a storage device is provided. The storage device is in communication with a host through a SATA bus. The data transmission control method includes the following steps. Firstly, a X_RDY primitive is issued from the storage device to the host. After a R_RDY primitive from the host is received by the from the storage device, a first frame is transmitted to the host. After the first frame is completely transmitted and in a specified time period before a second frame is transmitted, plural SYNC primitives are issued from the storage device to the host. If the host does not issue the X_RDY primitive in the specified time period, the second frame is transmitted to the host.

Abstract: A data transmission control method for a storage device is provided. The storage device is in communication with a host through a SATA bus. The data transmission control method includes the following steps. Firstly, a X_RDY primitive is issued from the storage device to the host. After a R_RDY primitive from the host is received by the from the storage device, a first frame is transmitted to the host. After the first frame is completely transmitted and in a specified time period before a second frame is transmitted, plural SYNC primitives are issued from the storage device to the host. If the host does not issue the X_RDY primitive in the specified time period, the second frame is transmitted to the host.

Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. In some embodiments, a semiconductor structure includes a substrate, a first lightly doped drain (LDD), a second LDD, an interface layer (IL), a high-k stack, a gate region, a dummy poly region, a first hard mask (HM) region, a second HM region, and a seal spacer region. The HK stack has a HK stack width and the gate region has a gate region width that is less than or substantially equal to the HK stack width. Because of the increased width of the HK stack, some of the HK stack likely overlaps some of the first LDD or the second LDD. In this manner, a saturation current and a threshold voltage associated with the semiconductor structure are improved. The increased width of the HK stack also protects more of the IL during LDD implanting.

Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: Novel use of small molecules, particularly indolyl and indolinyl hydroxamates is disclosed herein. The indolyl and indolinyl hydroxamates are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating a patient suffering from heart failure or neuronal injury.

Abstract: The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost.

Abstract: A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode.