Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening.

Abstract: A 3D bonded semiconductor device, which includes a first semiconductor device, a second semiconductor device, an isolation layer, a damascene structure, a barrier layer and a metal layer. The first semiconductor device includes a first substrate and a first conductive pad. The second semiconductor device includes a second substrate and a second conductive pad. The isolation layer covers on a backside of the second semiconductor device. The damascene structure includes a first via hole and a second via hole that respectively land on the first conductive pad and the second conductive pad at the same time, in which a first critical dimension of the first via hole is different from a second critical dimension of the second via hole. The barrier layer forms on the side-walls of the first via hole and the second via hole. The metal layer fills the damascene structure.

Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

Abstract: A semiconductor device and method of manufacturing thereof are provided. The semiconductor device includes a substrate, a first dielectric layer, an isolation layer, a conductor and a liner layer. The substrate has a top surface and a bottom surface opposite the top surface. The first dielectric layer is on the bottom surface of the substrate, in which the first dielectric layer comprises an interconnect structure disposed therein. The isolation layer is on the top surface of the substrate. The conductor is disposed in the substrate and covers a portion of the isolation layer, in which the conductor includes a first portion connected to the interconnect structure and a second portion on the first portion, in which the first portion has a width greater than a width of the second portion. The liner layer is disposed between the substrate and the conductor.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.

Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes steps of providing a stack structure, wherein the stack structure comprises a nitride layer, a first layer, a stop layer, a second layer, and a first oxide layer stacked in sequence; forming a third layer on the first oxide layer; patterning the third layer to obtain a line-and-space pattern comprising a plurality of first lines and a plurality of first spaces; forming a second oxide layer on the line-and-space pattern; removing the second oxide layer on the first lines; removing the first lines to form a plurality of second spaces; and etching the first oxide layer, the second layer, and the stop layer via the second spaces to form a plurality of second lines.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes steps of providing a stack structure, wherein the stack structure comprises a nitride layer, a first layer, a stop layer, a second layer, and a first oxide layer stacked in sequence; forming a third layer on the first oxide layer; patterning the third layer to obtain a line-and-space pattern comprising a plurality of first lines and a plurality of first spaces; forming a second oxide layer on the line-and-space pattern; removing the second oxide layer on the first lines; removing the first lines to form a plurality of second spaces; and etching the first oxide layer, the second layer, and the stop layer via the second spaces to form a plurality of second lines.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.