Patents by Inventor Yi Ju

Yi Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220045426
    Abstract: An interlaced array antenna includes first and second groups of antenna units, which are of the same size in the same group and different sizes in different groups. Each antenna unit is polygon-shaped with even-numbered edges, and has feed-in terminal and coupling terminal at two corners. A preceding one and a succeeding one of the antenna units included in the first group are interconnected via a specified one of the antenna units in the second group. An input signal is transmitted through the feed-in terminal and then the coupling terminal of the preceding antenna unit, the feed-in terminal and then the coupling terminal of the specified antenna unit, and the feed-in terminal and then the coupling terminal of the succeeding antenna unit in sequence. Configurations of adjacent two antenna units in the same group are identical once one of them is flipped about the x-axis.
    Type: Application
    Filed: September 28, 2020
    Publication date: February 10, 2022
    Inventors: YI JU LEE, RONG-FA KUO
  • Patent number: 11244950
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 8, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Jhen-Yu Tsai, Cheng-Han Yang, Yi-Ju Chen
  • Patent number: 11241157
    Abstract: An upper gastrointestinal bleeding monitoring system includes a detection device and a signal processing device to determine bleeding condition of an upper gastrointestinal tract by using relation of time and intensity ratios of RGB three primary colors. The detecting device is placed to the upper gastrointestinal tract of a patient via his/her mouth or nasal passage and then stay the upper gastrointestinal tract for several days for detection of bleeding. The signal processing device may receive and display signal from the detection device to help medical professionals check if bleeding occurs in an upper gastrointestinal tract. Moreover, a procedure of determination of bleeding in an upper gastrointestinal tract with the upper gastrointestinal bleeding monitoring system is described.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 8, 2022
    Assignee: MediVisionTech Co., Ltd
    Inventors: Chiao-Hsiung Chuang, Chien-Cheng Chen, Yi-Ju Chen
  • Patent number: 11228976
    Abstract: Various solutions for power saving for New Radio (NR) carrier aggregation in mobile communications are described. An apparatus receives, from a wireless network, a trigger signal. The apparatus switches between a first bandwidth part (BWP) and a second BWP of at least two BWPs for a secondary cell (SCell) in response to receiving the trigger signal. No physical downlink control channel (PDCCH) monitoring is configured for the first BWP while PDCCH monitoring is configured for the second BWP.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 18, 2022
    Inventors: Wei-De Wu, Yi-Ju Liao, Chi-Hsuan Hsieh
  • Publication number: 20210351282
    Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Cheng-Yi PENG, Wen-Yuan CHEN, Wen-Hsing HSIEH, Yi-Ju HSU, Jon-Hsu HO, Song-Bor LEE, Bor-Zen TIEN
  • Publication number: 20210320778
    Abstract: A method for enhancing Bandwidth Part (BWP) operation towards Secondary Cell (SCell) dormancy indication is proposed. A User Equipment (UE) detects a Downlink Control Information (DCI) format including an SCell dormancy indication that indicates an active BWP change for a serving cell. The UE performs BWP switching for the serving cell in response to the DCI format. The UE stops transmission or reception in the serving cell during a time duration from a slot containing a last symbol of the DCI format, wherein the time duration includes a first period of time of delay for the BWP switching and a second period of time of interruption to other active serving cells.
    Type: Application
    Filed: March 11, 2021
    Publication date: October 14, 2021
    Inventors: Chi-Hsuan Hsieh, Yi-Ju Liao, Wei-De Wu
  • Patent number: 11139203
    Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
  • Publication number: 20210280742
    Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first and second insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second protrusions covering first and second portions respectively, and a first recession exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first protrusion to contact the semiconductor structure. The second conductive portion is disposed on the second protrusion to contact the third portion through the first recession. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.
    Type: Application
    Filed: September 26, 2020
    Publication date: September 9, 2021
    Inventors: Pei-Shiu TSAI, Yi-Ju CHEN, Nai-Wei HSU, Wei-Chang YU
  • Publication number: 20210272901
    Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.
    Type: Application
    Filed: October 29, 2020
    Publication date: September 2, 2021
    Inventors: Kuo-Chiang Tsai, Yi-Ju Chen, Jyh-Huei Chen
  • Patent number: 11101441
    Abstract: A quantum dot light-emitting diode includes a substrate, an anode electrode layer, a cathode electrode layer, a light-emitting layer, and an electron blocking layer. The anode electrode layer is disposed on the substrate. The cathode electrode layer is disposed on the anode electrode layer. The light-emitting layer is disposed between the cathode electrode layer and the anode electrode layer. The light-emitting layer includes a plurality of first particles. The electron blocking layer is disposed between the light-emitting layer and the anode electrode layer. The electron blocking layer includes a plurality of second particles. The first particles and the second particles are quantum dots. A size of the second particles is smaller than a size of the first particles.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 24, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Ming-Cheng Kuo, Yao-Shan Chang, Po-Liang Chen, Chin-Cheng Tsai, Yi-Ju Hsiao, Ya-Pei Kuo
  • Patent number: 11082385
    Abstract: The current disclosure is directed towards systems and methods for automatically distributing an event comprising a plurality of key-value pairs, to a plurality of event subscribers, based on the plurality of key-value pairs satisfying one or more Boolean filters uniquely corresponding to one or more of the event subscribers, which may enable an increase in event distribution efficiency. In one example, this may increase event distribution efficiency by enabling a reduction in data exposure, as an event subscriber may receive only those events which satisfy a Boolean filter defined by the subscriber, and registered with the event conduit, and therefore, broadcast of events to uninterested subscribers may be reduced. Subscribers may specify interest in as broad, or as narrow a range of events as they wish, and thereby a more efficient match between subscriber interest and which events are distributed to that user may be enabled.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 3, 2021
    Assignee: CAMBIA HEALTH SOLUTIONS, INC.
    Inventors: Gaurav Dinesh Kalmady, Sriram Krishnan, Yi Ju Tsai
  • Publication number: 20210228657
    Abstract: An isolated lactic acid bacteria strain: Bifidobacterium longum subsp. longum OLP-01 strain for increasing exercise performance and ameliorating fatigue is disclosed. A variety of animal experiments have proved that OLP-01 not only effectively improves muscle strength and swimming endurance but also significantly reduces fatigue-related biochemical indicators, including blood lactate, blood urea nitrogen and the activity of creatine kinase.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Chi-Chang HUANG, Wei-Ling CHEN, Mon-Chien LEE, Yi-Ju HSU, Hsieh-Hsun HO, Shin-Yu TSAI, Wen-Yang LIN, Yi Wei KUO
  • Publication number: 20210219570
    Abstract: A circular integrated ecological breeding and planting system including a plurality of units capable of growing vegetables, producing worms, breeding and raising chickens, and growing seaweed is provided to collectively construct a simplified simulated food. It not only unifies the lower and upper ecological food chains, but also minimizes pollution and undesirable waste. The system is particularly suitable for enclosed and intensive production within a single enclosed building to greatly reduce the production cost. This proposed eco-agricultural model has applications beyond its current configuration and can be applied to grow other plants, and to breed and raise other animals in the future.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 22, 2021
    Inventor: YI JU CHUNG
  • Patent number: 11069791
    Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11067764
    Abstract: An optical transceiver includes a receptacle, a ferrule and a ferrule fastening component. The receptacle includes a supporting portion and an inset portion connected with each other. The ferrule is disposed within the inset portion. The ferrule fastening component is disposed on the receptacle. The ferrule fastening component includes a first holding portion, a cap and a second holding portion connected together. The cap is located between the first holding portion and the second holding portion. The first holding portion touches the supporting portion, the second holding portion touches the ferrule, and the cap covers a first area of a top surface of the receptacle.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: July 20, 2021
    Assignee: Prime World International Holdings Ltd.
    Inventors: Ting-Jhang Liao, YI-Ju Wang, Ming-You Lai
  • Publication number: 20210202734
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Yi-Ju CHEN, Jyh-Huei CHEN
  • Patent number: 11011276
    Abstract: A method for establishing a computer-aided data interpretation model for immune diseases by immunomarkers and visualization is revealed. First combine a plurality of immunomarkers into an immunomarker panel. Then collect test data of a plurality of subjects measured by the immunomarker panel, and disease diagnosis information of the subjects for establishment of an immunomarker-panel testing database. Next new subjects are tested by the immunomarker panel. The data obtained and the corresponding information in the immunomarker-panel testing database are processed by unsupervised machine learning algorithm to get a computer-aided data interpretation model showing comparison of case distribution patterns. The method provides real-time analysis of multiple data to medical professionals for their reference. Thereby the correctness, the timeliness and the reproducibility of the interpretation result for the diagnosis and treatment of immune diseases are all improved.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 18, 2021
    Assignees: CHANG GUNG MEMORIAL HOSPITAL, LINKOU, CHANG GUNG UNIVERSITY
    Inventors: Chun-Hsien Chen, Yi-Ju Tseng, Hsin-Yao Wang, Wan-Ying Lin, Chih-Kuang Chen
  • Publication number: 20210144638
    Abstract: Various solutions for determining monitoring occasion for power saving signal with respect to user equipment and network apparatus in mobile communications are described. An apparatus may receive a configuration of at least one search space set for power saving signal. The apparatus may determine at least one monitoring occasion of the search space set according to a starting point and a monitoring duration. The apparatus may monitor a power saving signal within the monitoring occasion. The apparatus may determine whether to wake up from a power saving mode according to the power saving signal.
    Type: Application
    Filed: October 6, 2020
    Publication date: May 13, 2021
    Inventors: Yi-Ju Liao, Wei-De Wu
  • Patent number: 10990843
    Abstract: A method and an electronic device for enhancing efficiency of searching for a region of interest in a virtual environment are provided. The virtual environment includes a visible scene and an invisible scene. A picture-in-picture (PIP) is displayed in the visible scene as a directional guidance or distance hint related to the region of interest in the invisible scene, thereby saving time and enhancing efficiency of searching for the region of interest.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 27, 2021
    Assignees: National Taiwan University, Mediatek Inc.
    Inventors: Yung-Ta Lin, Yi-Chi Liao, Shan-Yuan Teng, Yi-Ju Chung, Li-Wei Chan, Bing-Yu Chen
  • Patent number: 10982274
    Abstract: Disclosed are methods for nucleic acid amplification wherein nucleic acid templates, beads, and amplification reaction solution are emulsified and the nucleic acid templates are amplified to provide clonal copies of the nucleic acid templates attached to the beads. Also disclosed are kits and apparatuses for performing the methods of the invention.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 20, 2021
    Assignee: Roche Molecular Systems, Inc.
    Inventors: Jan Berka, Yi-Ju Chen, John H. Leamon, Steven Lefkowitz, Kenton L. Lohman, Vinod B. Makhijani, Jonathan M. Rothberg, Gary J. Sarkis, Maithreyan Srinivasan, Michael P. Weiner