Patents by Inventor Yi Liao

Yi Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200248862
    Abstract: An electronic device including a base, a display and a functional assembly is provided. The display is movably connected to the base and adapted to act between a lower position and an upper position relative to the base. The functional assembly is movably connected to the base and adapted to act between a first state and a second state relative to the base. When the display acts to the upper position from the lower position, the functional assembly acts to the second state from the first state, and when the functional assembly acts to the first state from the second state, the display acts to the lower position from the upper position.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 6, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chun-Yi Ho, Huai-Te Tseng, Ming-Chung Peng, Chen-Yu Liao, Che-Wei Liang, Shih-Ching Hsu
  • Publication number: 20200251395
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulating layer encapsulates the electronic component and the conductive elements. The encapsulating layer is formed with recessed portions corresponding in position to the conductive elements. A gap is formed between the conductive elements and the recessed portions.
    Type: Application
    Filed: July 2, 2019
    Publication date: August 6, 2020
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Patent number: 10727117
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 10726899
    Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Wayne I. Kinney, Yi Fang Lee, Manzar Siddik
  • Patent number: 10712782
    Abstract: A front cover assembly includes a frame, a cover glass, and a waterproof glue. The frame has a receiving cavity. The cover glass is partially received in the frame. The cover glass has a lateral face facing the frame. The cover glass has a step portion located at the lateral face. A first gap is defined between a first face of the step portion of the cover glass and a first wall of the frame, and a second gap is defined between a second face of the step portion of the cover glass and a second wall of the frame. A waterproof glue fills the first and second gaps. The first and second faces of the step portion from an obtuse angle therebetween, which faces the first and second walls of the frame. The present disclosure also relates to a terminal.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 14, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Yimei Tang, Yong Li, Hong Zou, Yi Sun, Wei Zhang, Xinfeng Liao, Zhiqin Hu, Xiaohui Wang, Bing Liu, Yuchu Xu, Wei Chen
  • Patent number: 10712505
    Abstract: An optical fiber connector configured for engaging with an external optical fiber connector includes a fiber core, a connector body, a coupling tube, and at least one coupling holder. The connector body has a first end portion and a second end portion, and the first end portion connects and fixes the fiber core. The second end portion is depressed inwardly to define a coupling space, and the external optical fiber connector is detachably plugged into the coupling space and coupled with the fiber core. The coupling tube is disposed in the connector body, and a portion of the coupling tube is located in the coupling space. One end portion of the fiber core is inserted in the coupling tube. The coupling holder is disposed in the coupling space, and corresponding to the coupling tube.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 14, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Cheng-Yi Liao, Cheng-Chung Chen, Wei-Chun Tsao
  • Patent number: 10705238
    Abstract: The present disclosure discloses a method and an apparatus for processing seismic data, and belongs to the field of geological surveys. The method comprises: stacking seismic trace gathers in a predetermined range among S seismic trace gathers after a Normal Move Out (NMO) correction processing to obtain a model trace, S being an integer; calculating a correlation coefficient of each seismic trace gather with the model trace, and selecting a K-th seismic trace gather with a maximum correlation coefficient; calculating an optimum point of each seismic trace gather from the K-th seismic trace gather to two sides orderly; and performing a residual NMO correction of the seismic trace gathers according to the optimum points.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 7, 2020
    Assignee: PETROCHINA COMPANY LIMITED
    Inventors: Guangrong Zhang, Fusen Xiao, Qi Ran, Shirong Zhang, Yi Yu, Qi Liao, Bo Ma, Han Liang, Kang Chen, Xuan Zhang, Xiaomin Lu
  • Patent number: 10707785
    Abstract: A simple rugged motor has a stator and a rotor formed by stacked silicon steel sheets operates by having a plurality of major and minor coil windings of the stator individually electrified under signals of a control unit, so as to steadily drive a rotor thereof. The simple rugged motor further has an orbit coupling balance assembly engaging an orbiting scroll for a corresponding fixed scroll disposed in a compression chamber to orbit for air compression, so as to form a scroll compressor. Or the simple rugged motor has a coupling assembly engaging a female screw compressor rotor to compress the air by a rotatable male screw compressor rotor disposed in a compression chamber, so as to form a screw compressor.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 7, 2020
    Inventor: Pen-Yi Liao
  • Publication number: 20200212290
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 2, 2020
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 10689362
    Abstract: A compound, capable of inhibiting kinases, for the treatments of diseases or disorders mediated by such kinases, has a structure of formula (I): or a stereoisomer, a tautomer, a pharmaceutically acceptable salt thereof. The compound can be used in the treatments of diseases or conditions mediated by CSF-1R, c-KIT, FLT3, or PDGFR kinases. Such diseases or conditions may include cancers, autoimmune diseases, and bone resorptive diseases.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: June 23, 2020
    Assignee: Development Center for Biotechnology
    Inventors: Shao-Zheng Peng, Chu-Bin Liao, Hung-Kai Chen, Chen-Hsuan Ho, Hung-Jyun Huang, Shian-Yi Chiou
  • Patent number: 10688193
    Abstract: The invention provides a pH-sensitive linker that can simultaneously bind metallic nanoparticles and one or more agents with various molecular size. The linker of the invention can deliver the agents into cells involved in disease processes or close to cells so that the agents can selectively target and effect on the cells. The target delivery provided by the linker of the invention can be used for example for disease sensing, imaging, drug delivery, and therapy.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 23, 2020
    Assignee: GNT BIOTECH & MEDICALS CORPORATION
    Inventors: Yu-Jung Liao, Wei-Jan Huang, Chia-Nan Chen, Huan-Yu Lin, Ching-Yi Lin, Meng-Ju Tsai, Wan-Yi Hsu, Li-Ling Chi, Ye-Su Chao, Yi-Hong Wu
  • Publication number: 20200182233
    Abstract: A MEMS pump module includes a microprocessor and a MEMS chip. The microprocessor outputs a constant voltage and a variable voltage. The MEMS chip includes a chip body, a plurality of MEMS pumps and at least one common electrode. The plurality of MEMS pumps are disposed on the chip body, and each MEMS pump includes a first electrode and a second electrode. The at least one common electrode is disposed on the chip body and electrically connected to the second electrodes of the plurality of MEMS pumps. The microprocessor is electrically connected to the first electrodes of the plurality of MEMS pumps and the at least one common electrode so as to transmit the constant voltage to the at least one common electrode and transmit the variable voltage to the first electrodes of the plurality of MEMS pumps.
    Type: Application
    Filed: November 20, 2019
    Publication date: June 11, 2020
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han, Chun-Yi Kuo
  • Patent number: 10680120
    Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 9, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ching-Yi Hsu, Shih-Hao Liu, Wu-Hsi Lu, Yun-Chou Wei, Chih-Cherng Liao
  • Patent number: 10672737
    Abstract: Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 ?m.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Publication number: 20200165446
    Abstract: A thermosetting resin composition comprises a thermosetting polybutadiene resin, a thermosetting polyphenylene ether resin that is ended with styrene and acrylate in a weight ratio of 0.5-1.5 as reactive functional groups, a thermoplastic resin that serves to set desired heat resistance, flowability and filling performance, a compound cross-linking initiator composed of peroxides of different half-life temperatures to effectively improve its crosslink density during its thermal curing process; particularly the composition after cured has a low dielectric constant, a low dielectric dissipation factor, a high Tg, and high rigidity, and the prepreg made thereof is easy to cut.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Te-Chao LIAO, Ying-Te HUANG, Hao-Sheng CHEN, Hung-Yi CHANG, Chia-Lin LIU
  • Publication number: 20200167182
    Abstract: A method for generating a nested container with no intersection and same layer full coverage, including: giving a right undirected graph G(V, E, W) and network measurement index set {Ti} for dividing nodes in G, each network measurement index Ti corresponding to a Ci layer container set {Ci k}; deleting an edge weighing greater than Ti, and segmenting G into subgraphs, each a connected component; setting all nodes in the subgraph Gcm not in the Ci layer container as set L; selecting one node from set L as current anchor aj; starting with anchor aj, performing breadth-first search on all nodes in L and Ci+1 layer container containing aj with the path communicated therewith less than Ti forming a Ci layer container with anchor aj; setting j?=j+1, determining whether L is a null set; setting m=m+1, determining whether all subgraphs are processed; setting i=i-1, and determining whether i=1 is satisfied.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 28, 2020
    Applicants: INSTITUTE OF ACOUSTICS, CHINESE ACADEMY OF SCIENCES, BEIJING HILI TECHNOLOGY CO., LTD
    Inventors: Yiqiang SHENG, Jinlin WANG, Yi LIAO, Xiaozhou YE, Gang CHENG, Haojiang DENG, Lingfang WANG
  • Publication number: 20200165434
    Abstract: A fluorocarbon resin composition is applicable to produce a prepreg for use in making a high-frequency circuit board, including a polytetrafluoroethylene resin; a fluorine-containing copolymer of poly fluoroalkoxy or fluorinated ethylene propylene; inorganic powders and an impregnation additive such as hydroxyethyl cellulos; resulted in that the prepreg is capable of increasing a plurality of times for proceeding impregnation-coating, the surface defects prone to occur on a fluorocarbon prepreg during drying, baking and sintering after impregnation are therefore improved at the same time.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Te-Chao LIAO, Ying-Te HUANG, Chih-Kai CHANG, Hung-Yi CHANG, Hao-Sheng CHEN, Chia-Lin LIU
  • Publication number: 20200165501
    Abstract: A fluorocarbon resin composition is applicable to produce high-frequency circuit boards including a polytetrafluoroethylene resin; a fluorine-containing copolymer such as poly fluoroalkoxy and fluorinated ethylene propylene; low molecular-weight PTFE micro-powders and inorganic powders; in particular the temperature of pressing copper foil substrates is lowered from 350° C. to 250° C. via a lowering temperature rate of 1 to 4° C./min to improve the crystallinity of the fluorocarbon resin composition as well as improve the copper foil substrate with a high thermal conductivity and a wide range of dielectric constant.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Te-Chao LIAO, Hao-Sheng CHEN, Chih-Kai CHANG, Hung-Yi CHANG
  • Publication number: 20200163166
    Abstract: An embodiment of the disclosure provides a heater package including a substrate, a first barrier layer, at least one heater, and a second barrier layer. The first barrier layer is disposed on a surface of the substrate and has a first treatment layer on a side away from the substrate. The heater is disposed on the substrate and includes a heating layer and at least one electrode. The at least one electrode and the heating layer contact with each other. The second barrier layer covers an upper surface and a sidewall of the heater and has a second treatment layer on an opposite side or the side away from the substrate. A ratio of a thickness of the first treatment layer to a thickness of the first barrier layer and a ratio of a thickness of the second treatment layer to a thickness of the second barrier layer range from 0.03 to 0.2.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Ching Kuo, Chien-Chang Hung, Hong-Ming Dai, Jane-Hway Liao, Hung-Yi Chen, Shu-Tang Yeh
  • Publication number: 20200156737
    Abstract: The disclosure provides a bicycle front derailleur including a fixing component, a chain guiding component, a linkage assembly, a battery assembly, two terminals, a circuit board assembly and a driving module. Two opposite ends of the linkage assembly are respectively and pivotally disposed on the fixing component and the chain guiding component. The battery assembly includes a battery holder and a battery. The battery holder is disposed on the fixing component, and the battery holder has a battery slot. One terminal is disposed in the battery slot, and the battery is removably inserted into the battery slot and is electrically connected to the terminal. The circuit board assembly is disposed on the fixing component and electrically connected to the other terminal. The terminals are electrically connected to each other. The driving module is disposed on the fixing component and electrically connected to the circuit board assembly.
    Type: Application
    Filed: December 4, 2018
    Publication date: May 21, 2020
    Inventors: Bo-Yi Liao, Yu-Ming Huang, Tzung Ye Wu