Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a metallic housing, a first feed portion, and a second feed portion. The metallic housing includes a metallic side frame and a metallic back board. The metallic side frame defines a slot, and first and second gaps. The metallic side frame between the first gap and one end of the slot forms a first radiation portion. The second gap divides the first radiation portion into first and second radiation sections. The first feed portion feeds current and signal to the first radiation section, and the first radiation section works in a GPS mode and a WIFI 2.4 GHz mode. The second feed portion feeds current and signal to the second radiation section, and the second radiation section works in a WIFI 5 GHz mode.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

Abstract: Examples of control of detachable camera devices are discussed. A detachable camera device may include a camera and an illumination module. Based on user inputs provided on an apparatus to which the device is detachably coupled, the position of the camera and the intensity of light provided by the illumination module can be changed. The device may include a controller to receive the user inputs from the apparatus and control the camera and the illumination module.

Abstract: In one example, an electronic device is described, which includes a position activator, a database including display positions associated with a plurality of users, and a processor coupled to the position activator and the database. The processor may retrieve a display position corresponding to a user operating the electronic device from the database and trigger the position activator to set a viewing position of a display of the electronic device based on the retrieved display position.

Abstract: An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Abstract: An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Abstract: In one example, an electronic device is described, which includes a position activator, a database including display positions associated with a plurality of users, and a processor coupled to the position activator and the database. The processor may retrieve a display position corresponding to a user operating the electronic device from the database and trigger the position activator to set a viewing position of a display of the electronic device based on the retrieved display position.

Abstract: A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery unit and configured to generate a data clock signal and an edge clock signal according to a phase signal and a reference clock signal. The clock and data recovery unit is configured to generate the phase signal according to a data signal, the data clock signal and the edge clock signal. The spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and to transmit the reference clock signal to the first phase interpolator. The spread spectrum clock tracking circuit is decoupled to the clock and data recovery loop.

Abstract: A receiving device includes a first calculating circuit, an error slicer, a data slicer, a second calculating circuit, and an equalization circuit. The first calculating circuit is configured to generate a calculating signal according to an equalized signal and a feedback signal. The error slicer is configured to generate an error signal according to the calculating signal. The data slicer is configured to generate a data signal according to the calculating signal. The second calculating circuit is configured to generate a first, a second, and a third equalization coefficient according to the data signal and the error signal. The equalization circuit is configured to generate the feedback signal according to the first, the second, and the third equalization coefficient. A gain value of the equalization circuit is associated with the first equalization coefficient. A time constant of the equalization circuit is associated with the second and the third equalization coefficient.

Abstract: A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery unit and configured to generate a data clock signal and an edge clock signal according to a phase signal and a reference clock signal. The clock and data recovery unit is configured to generate the phase signal according to a data signal, the data clock signal and the edge clock signal. The spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and to transmit the reference clock signal to the first phase interpolator. The spread spectrum clock tracking circuit is decoupled to the clock and data recovery loop.

Abstract: A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.

Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.

Abstract: A receiver is provided. The receiver includes a CTLE receiving a received signal, and generating a first equalized signal by processing the received signal according to a pole and a boost level; a slicing circuit coupled to the CTLE, generating a data signal according to the first equalized signal and a feedback equalization signal; a DFE coupled to the slicing circuit, generating the feedback equalization signal by processing the data signal according to a DFE coefficient set. Furthermore, the boost level is adjusted according to a first DFE coefficient of the DFE coefficient set, while the pole is adjusted according to the second and third DFE coefficients.

Abstract: An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.