Patents by Inventor Yi-Lin Lee
Yi-Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9584304Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.Type: GrantFiled: March 30, 2015Date of Patent: February 28, 2017Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Hsu Chien, Yi-Lin Lee, Ju-Chieh Wang
-
Publication number: 20160294538Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.Type: ApplicationFiled: March 30, 2015Publication date: October 6, 2016Inventors: Ting-Hsu Chien, Yi-Lin Lee, Ju-Chieh Wang
-
Patent number: 9438450Abstract: A receiver is provided. The receiver includes a CTLE receiving a received signal, and generating a first equalized signal by processing the received signal according to a pole and a boost level; a slicing circuit coupled to the CTLE, generating a data signal according to the first equalized signal and a feedback equalization signal; a DFE coupled to the slicing circuit, generating the feedback equalization signal by processing the data signal according to a DFE coefficient set. Furthermore, the boost level is adjusted according to a first DFE coefficient of the DFE coefficient set, while the pole is adjusted according to the second and third DFE coefficients.Type: GrantFiled: July 2, 2015Date of Patent: September 6, 2016Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Juh Kang, Yu-Chu Chen, Yi-Lin Lee
-
Patent number: 9312819Abstract: An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.Type: GrantFiled: March 24, 2015Date of Patent: April 12, 2016Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yen-Chung Chen, Tsai-Ming Yang, Yi-Lin Lee
-
Publication number: 20150043113Abstract: ESD clamp circuit is provided, including an RC circuit, a first transistor, a second transistor, an ESD conduction unit and an inverter. The first transistor has a gate and a drain respectively coupled to the RC circuit and a control terminal of the ESD conduction unit. The inverter has an input terminal coupled to the control terminal. The second transistor has a drain and a gate respectively coupled to the control terminal and an output terminal of the inverter. The gates of the first and second transistors are isolated; also the output terminal and the gate of the first transistor are isolated.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Tsai-Ming Yang, Yen-Chung Chen, Jen-Tai Hsu, Yi-Lin Lee
-
Patent number: 8928380Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.Type: GrantFiled: March 19, 2014Date of Patent: January 6, 2015Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., LtdInventors: Tsai-Ming Yang, Yen-Chung Chen, Yi-Lin Lee, Jen-Tai Hsu
-
Publication number: 20140285248Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.Type: ApplicationFiled: March 19, 2014Publication date: September 25, 2014Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Tsai-Ming Yang, Yen-Chung Chen, Yi-Lin Lee, Jen-Tai Hsu
-
Patent number: 8547149Abstract: This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.Type: GrantFiled: March 30, 2011Date of Patent: October 1, 2013Assignee: Global Unichip CorporationInventors: Fu-Tai An, Jen-Tai Hsu, Yi-Lin Lee
-
Patent number: 8532314Abstract: An audio volume control circuit includes a signal intensity calculating circuit for generating a first signal intensity value corresponding to a signal intensity corresponding to an audio channel data; a low-pass filter for filtering the first signal intensity to generate a second signal intensity value; an averaging unit for averaging the second signal intensity value and previous M?1 second signal intensity values to obtain a third signal intensity value, with M being a natural number greater than 1; a gain calculating circuit for obtaining an original gain value according to the third signal intensity value with reference to the adjustment condition; a buffer for temporarily storing the audio channel data; and an audio volume adjusting circuit for generating an adjustment gain value according to the original gain value to adjust the audio channel data stored in the buffer.Type: GrantFiled: November 2, 2010Date of Patent: September 10, 2013Assignee: Mstar Semiconductor, Inc.Inventors: Yi-Lin Lee, Bo-Ju Chen, Zhi-Ren Chang
-
Publication number: 20120020203Abstract: This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.Type: ApplicationFiled: March 30, 2011Publication date: January 26, 2012Applicant: Global Unichip CorporationInventors: Fu-Tai An, Jen-Tai Hsu, Yi-Lin Lee
-
Publication number: 20110158432Abstract: An audio volume control circuit includes a signal intensity calculating circuit for generating a first signal intensity value corresponding to a signal intensity corresponding to an audio channel data; a low-pass filter for filtering the first signal intensity to generate a second signal intensity value; an averaging unit for averaging the second signal intensity value and previous M?1 second signal intensity values to obtain a third signal intensity value, with M being a natural number greater than 1; a gain calculating circuit for obtaining an original gain value according to the third signal intensity value with reference to the adjustment condition; a buffer for temporarily storing the audio channel data; and an audio volume adjusting circuit for generating an adjustment gain value according to the original gain value to adjust the audio channel data stored in the buffer.Type: ApplicationFiled: November 2, 2010Publication date: June 30, 2011Applicant: MStar Semiconductor, Inc.Inventors: Yi-Lin Lee, Bo-Ju Chen, Zhi-Ren Chang