Abstract: A Bluetooth service estimation apparatus and a Bluetooth service estimation method thereof are provided. The Bluetooth service estimation apparatus listens to data packets transmitted between the Bluetooth host and the remote Bluetooth device, and determines a Bluetooth service type between the Bluetooth host and the remote Bluetooth device according to contents of the data packets. The Bluetooth service estimation apparatus transmits the Bluetooth service type to a packet traffic arbitration module of a Wi-Fi host so that the Wi-Fi host determines a weight of network resources according to the Bluetooth service type, and decides a utilization rate of an antenna based on the weight of the network resources.

Abstract: An adaptive filter is disclosed, having a plurality of computation groups, a plurality of computation circuits, a summation circuit, a slicer circuit, an updating circuit, and a control circuit. Each computation group corresponds to an equalization parameter and has a plurality of memory cells. When the corresponding equalization parameter of a computation group is greater than a predetermined value, the control circuit configures the computation group and the computation circuit to collaboratively generate an output of the computation group. The summation circuit sums up the outputs of the computation groups to produce a filter output. The slicer circuit generates a slicer output according to the filter output. The updating circuit updates the equalization parameters according to the filter output and the slicer output.

Abstract: An equalizer and an equalizing method for equalizing a received signal, where the received signal includes at least one primary interference and a plurality of secondary interferences. The Viterbi equalizer includes a filter module for filtering out the secondary interferences from the received signal to generate a filtered signal, a serial to parallel converter, coupled to the filter module, for generating a plurality of sequences according to the filtered signal, and a Viterbi equalizing module, coupled to the serial to parallel converter, for respectively equalizing the plurality of sequences to generate a plurality of equalized sequences. The architecture of the Viterbi equalizing module is greatly simplified thereby reducing the calculation activity of the Viterbi equalizer as well as maintaining its efficiency.

Abstract: A complex divider utilized for dividing a first complex number by a second complex number to generate a computing result includes a computing unit and a dividing unit. The computing unit is utilized for receiving the first complex value and the second complex value, generating a third complex value according to the first complex value and the second complex value, and generating a real number according to the second complex value. The dividing unit is coupled to the computing unit, and is utilized for receiving the third complex value and the real number and dividing the third complex value by the real number to obtain the computing result.

Abstract: An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences.

Abstract: A signal processing method by adding odd and even field SYNC data for neutralized effects including the steps of receiving an odd field SYNC data of an odd field, which is different at a certain data segment when compared with an even field SYNC data of an even field, and the even field SYNC data of the even field; adding the odd field SYNC data and the even field SYNC data to neutralize the odd and even field SYNC data so as to generate a combined odd and even field SYNC data; and performing a predetermined signal processing on an input signal according to the combined odd and even field SYNC data.

Abstract: A receiver includes a discrete Fourier transform unit, a frequency-domain equalizer, an inverse discrete Fourier transform unit, a time-domain equalizer and an output circuit. The discrete Fourier transform unit is utilized for performing a discrete Fourier transform operation upon a received signal to generate a frequency-domain signal. The frequency-domain equalizer is utilized for equalizing the frequency-domain signal to generate an equalized frequency-domain signal. The inverse discrete Fourier transform unit is utilized for performing an inverse discrete Fourier transform operation upon the equalized frequency-domain signal to generate a first equalized time-domain signal. The time-domain equalizer is utilized for equalizing the received signal to generate a second equalized time-domain signal. The output circuit is utilized for generating a third equalized time-domain signal according to the first equalized time-domain signal and the second equalized time-domain signal.

Abstract: An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences.

Abstract: A phase calibration circuit applied to at least one signal processing module group includes at least two phase calibration modules, a phase detection module and a filter module. An output node of a first phase calibration module is coupled to an input node of a first signal processing module, an input node of a second phase calibration module is coupled to an output node of the first signal processing module, and the first signal processing module receives a calibrated signal outputted from the first phase calibration module and generates a processed signal. The phase detection module is utilized for generating a phase error signal according to a calibrated signal of an Mth phase calibration module, where M is an integer equal to or greater than two. The filter module is utilized for generating at least a first and a second phase calibration signal according to the phase error signal.

Abstract: The equalizer presented includes a first feed-forward equalization module, a second feed-forward equalization module, and a phase error corrector. The first and the second feed-forward equalization modules respectively receives an input real-part component signal and an input imaginary-part component signal of a complex input signal and respectively equalizes the input real-part component signal and the input imaginary-part component signal to generate a first real-part component signal and a first imaginary-part component signal. The phase error corrector is coupled to the first and the second feed-forward equalization modules for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information.

Abstract: A complex divider utilized for dividing a first complex number by a second complex number to generate a computing result includes a computing unit and a dividing unit. The computing unit is utilized for receiving the first complex value and the second complex value, generating a third complex value according to the first complex value and the second complex value, and generating a real number according to the second complex value. The dividing unit is coupled to the computing unit, and is utilized for receiving the third complex value and the real number and dividing the third complex value by the real number to obtain the computing result.

Abstract: A communication signal receiver includes a feed-forward filter and a coefficient adjusting circuit. The feed-forward filter generates an estimated imaginary-part component signal according to a real-part component of a complex data signal by using tap coefficients of the feed-forward filter. The coefficient adjusting circuit adjusts the tap coefficients of the feed-forward filter according to a control information, wherein the control information comprises a phase error information. The phase error information changes as a phase of the complex data signal changes, wherein the phase is adjusted or not adjusted by the coefficient adjusting circuit.

Abstract: A receiver includes a discrete Fourier transform unit, a frequency-domain equalizer, an inverse discrete Fourier transform unit, a time-domain equalizer and an output circuit. The discrete Fourier transform unit is utilized for performing a discrete Fourier transform operation upon a received signal to generate a frequency-domain signal. The frequency-domain equalizer is utilized for equalizing the frequency-domain signal to generate an equalized frequency-domain signal. The inverse discrete Fourier transform unit is utilized for performing an inverse discrete Fourier transform operation upon the equalized frequency-domain signal to generate a first equalized time-domain signal. The time-domain equalizer is utilized for equalizing the received signal to generate a second equalized time-domain signal. The output circuit is utilized for generating a third equalized time-domain signal according to the first equalized time-domain signal and the second equalized time-domain signal.

Abstract: A signal processing method by adding odd and even field SYNC data for neutralized effects including the steps of receiving an odd field SYNC data of an odd field, which is different at a certain data segment when compared with an even field SYNC data of an even field, and the even field SYNC data of the even field; adding the odd field SYNC data and the even field SYNC data to neutralize the odd and even field SYNC data so as to generate a combined odd and even field SYNC data; and performing a predetermined signal processing on an input signal according to the combined odd and even field SYNC data.

Abstract: The equalizer presented includes a first feed-forward equalization module, a second feed-forward equalization module, and a phase error corrector. The first and the second feed-forward equalization modules respectively receives an input real-part component signal and an input imaginary-part component signal of a complex input signal and respectively equalizes the input real-part component signal and the input imaginary-part component signal to generate a first real-part component signal and a first imaginary-part component signal. The phase error corrector is coupled to the first and the second feed-forward equalization modules for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information.

Abstract: A communication signal receiver includes a feed-forward filter and a coefficient adjusting circuit. The feed-forward filter generates an estimated imaginary-part component signal according to a real-part component of a complex data signal by using tap coefficients of the feed-forward filter. The coefficient adjusting circuit adjusts the tap coefficients of the feed-forward filter according to a control information, wherein the control information comprises a phase error information. The phase error information changes as a phase of the complex data signal changes, wherein the phase is adjusted or not adjusted by the coefficient adjusting circuit.

Abstract: The present invention provides a method and apparatus for correcting symbol timing of a receiver. The receiver receives a signal transmitted by a transmitter based on a symbol period. The method includes: sampling the signal with a sampling period to generate N sampled data in series, wherein the sampling period is half the symbol period; from Kth data of the N sampled data, getting M data to serve as a first data set; performing a timing recovery algorithm upon the first data set to generate a first timing metric; from (Kth+1) data of the N sampled data, getting M data to serve as a second data set; performing the timing recovery algorithm upon the second data set to generate a second timing metric; and correcting the symbol timing according to the first and second timing metrics.

Abstract: An equalizer includes a tapped delay line and an adder. The tapped delay line includes a plurality of taps cascaded to each other. The tapped delay line receives an input signal, a plurality of tap control signals, and a plurality of tap coefficients and generates a plurality of multiplied signals. The plurality of taps is divided into a plurality of groups. The adder is coupled to the tapped delay line for adding the plurality of multiplied signals up to generate an output signal.

Abstract: A phase calibration circuit applied to at least one signal processing module group includes at least two phase calibration modules, a phase detection module and a filter module. An output node of a first phase calibration module is coupled to an input node of a first signal processing module, an input node of a second phase calibration module is coupled to an output node of the first signal processing module, and the first signal processing module receives a calibrated signal outputted from the first phase calibration module and generates a processed signal. The phase detection module is utilized for generating a phase error signal according to a calibrated signal of an Mth phase calibration module, where M is an integer equal to or greater than two. The filter module is utilized for generating at least a first and a second phase calibration signal according to the phase error signal.

Abstract: The present invention provides a method and circuit for equalizing and compensating IQ imbalance at the same time. The method includes: down-converting an RF signal to generate a baseband signal, and driving an adaptive equalizer to process the baseband signal for achieving equalization and IQ imbalance compensation simultaneously.