Equalizer and method applied thereto

The equalizer presented includes a first feed-forward equalization module, a second feed-forward equalization module, and a phase error corrector. The first and the second feed-forward equalization modules respectively receives an input real-part component signal and an input imaginary-part component signal of a complex input signal and respectively equalizes the input real-part component signal and the input imaginary-part component signal to generate a first real-part component signal and a first imaginary-part component signal. The phase error corrector is coupled to the first and the second feed-forward equalization modules for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information.

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Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an equalizer and a related method, and more particularly, to an apparatus and a related method for combining the equalizer with a phase error corrector to improve the performance of the equalizer.

2. Description of the Prior Art

In communication systems, inter-symbol interference (ISI) is a common phenomenon. The primary cause of ISI is multipath propagation. Hence, an equalizer is typically adopted in signal receivers for reducing effects resulted from multipath propagation during signal transmission.

When processing complex signals (such as a VSB signal) by adopting the equalizer, the performance of the equalizer will be restricted by the phase error existing between the signals of the equalizer if only a single equalizer is used for equalizing the real-part component of the complex signal. In addition, although the phase error of the signals processed by the equalizer is adjusted by adopting a phase error corrector, the performance of the equalizer may be poor since the phase error corrector only has a one-dimensional input (i.e., the real-part component). Hence, how to improve the performance of the equalizer has become one of the important topics of the field.

SUMMARY OF THE INVENTION

It is therefore one of the objectives of the claimed invention to provide an equalizer and a related method for solving the abovementioned problems.

According to an exemplary embodiment of the present invention, an equalizer is provided. The equalizer includes a first feed-forward equalization module, a second feed-forward equalization module, and a phase error corrector. The first feed-forward equalization module receives an input real-part component signal of a complex input signal and equalizes the input real-part component signal to generate a first real-part component signal. The second feed-forward equalization module receives the input imaginary-part component signal of the complex input signal and equalizes the input imaginary-part component signal to generate a first imaginary-part component signal. The phase error corrector is coupled to the first feed-forward equalization module and the second feed-forward equalization module for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information. The second feed-forward equalization module equalizes the input imaginary-part component signal according to tap coefficients adopted by the first feed-forward equalization module.

According to another exemplary embodiment of the present invention, a method applied to an equalizer is provided. The method includes the steps of receiving an input real-part component signal of a complex input signal, and equalizing the input real-part component signal to generate a first real-part component signal; receiving an input imaginary-part component signal of the complex input signal, and equalizing the input imaginary-part component signal to generate a first imaginary-part component signal; and adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an equalizer according to a first embodiment of the present invention.

FIG. 2 is a diagram of an equalizer according to a second embodiment of the present invention.

FIG. 3 is a flowchart illustrating a method applied to an equalizer according to an exemplary embodiment of the present invention.

FIG. 4 is a flowchart illustrating a method applied to an equalizer according to another exemplary embodiment of the present invention.

 DETAILED DESCRIPTION

FIG. 1 is a diagram of an equalizer 100 according to a first embodiment of the present invention. The equalizer 100 includes, but is not limited to, a first feed-forward equalization module 110, a second feed-forward equalization module 120, a phase error corrector 130, a first operator 140, a slicer 150, and a feedback equalization module 160. As shown in FIG. 1, the first feed-forward equalization module 110 receives an input real-part component signal xr[n] of a complex input signal x[n], and equalizes the input real-part component signal xr[n] to generate a first real-part component signal yr1[n]. The second feed-forward equalization module 120 receives an input imaginary-part component signal xi[n] of the complex input signal x[n], and equalizes the input imaginary-part component signal xi[n] to generate a first imaginary-part component signal yi1[n]. The phase error corrector 130 is coupled to the first feed-forward equalization module 110 and the second feed-forward equalization module 120 for adjusting a complex phase corresponding to the first real-part component signal yr1[n] and the first imaginary-part component signal yi1[n] to generate a second real-part component signal yr2[n] and a second imaginary-part component signal yi2[n] according to phase error information dr[n] and di[n]. In addition, the first operator 140 is coupled to the phase error corrector 130 for performing an operation on the second real-part component signal yr2[n] and a third real-part component signal yr3[n] to generate an output real-part component signal eqor[n]. The slicer 150 is coupled to the first operator 140 for performing a hard decision on the output real-part component signal eqor[n] to generate a detecting result Sd. The feedback equalization module 160 is coupled to the slicer 150 and the first operator 140 for equalizing the detecting result Sd to generate the third real-part component signal yr3[n].

Please note that the abovementioned complex input signal x[n] (including the input real-part component signal xr[n] and the input imaginary-part component signal xi[n]) can be a vestigial sideband (VSB) signal, but the present invention is not limited to this only and can be signals of other types. In addition, the equalizer 100 can be a decision feedback equalizer (DFE), but this should not be considered as limitations of the present invention and can be an equalizer of other types.

Please also note that each of the first feed-forward equalization module 110 and the second feed-forward equalization module 120 can be implemented by a tapped delay line equalizer, wherein the second feed-forward equalization module 120 equalizes the input imaginary-part component signal xi[n] according to the tap coefficients fr[n] adopted by the first feed-forward equalization module 110. In other words, the second feed-forward equalization module 120 and the first feed-forward equalization module 110 adopt the same tap coefficients fr[n] to equalize the input imaginary-part component signal xi[n] and the input real-part component signal xr[n] respectively. This is merely a preferred embodiment of the present invention, and other manners capable of achieving the same goal under obeying the spirit of the present invention should also belong to the scope of the present invention.

In this embodiment, the first operator 140 is implemented by an adder. The adder subtracts the third real-part component signal yr3[n] from the second real-part component signal yr2[n] to generate the output real-part component signal eqor[n]. But this is not meant to be a limitation of the present invention, and operators of other types can be adopted to implement the first operator 140.

As can be known from FIG. 1, the input real-part component signal xr[n] and the input imaginary-part component signal xi[n] are respectively equalized by the first feed-forward equalization module 110 and the second feed-forward equalization module 120, and thus the signals inputted to the phase error corrector 130 consist of two-dimensional inputs, that is, the first real-part component signal yr1, [n] and the first imaginary-part component signal yi1[n]. Therefore, not only can the efficiency of the phase error corrector 130 for adjusting the phase error be improved, but also can the performance of the equalizer 100 be promoted. Moreover, the output real-part component signal eqor[n] of the equalizer 100 can be obtained by processing the second real-part component signal yr2[n] outputted from the phase error corrector 130 according to its feedback circuits (i.e., the first operator 140, the slicer 150, and the feedback equalization module 160).

Certainly, the abovementioned equalizer 100 is merely a practicable embodiment of the present invention. In other embodiments, more functions are designated into the equalizer to improve its performance. Please refer to FIG. 2. FIG. 2 is a diagram of an equalizer 200 according to a second embodiment of the present invention. The architecture of the equalizer 200 shown in FIG. 2 is similar to the equalizer 100 shown in FIG. 1, and the differences between them are described below. The equalizer 200 further consists of a first delay 210, a filter 220, a second operator 230, a second delay 240, and a phase error estimator 250. The first delay 210 is coupled to the phase error corrector 130 for delaying the second imaginary-part component signal yi2[n] to generate a delayed second imaginary-part component signal ydi2[n]. The filter 220 is coupled to the feedback equalization module 160 for receiving the third real-part component signal yr3[n] and for generating an estimated imaginary-part component signal yi′[n] according to the third real-part component signal yr3[n]. After that, the second operator 230 performs an operation (such as a subtraction) on the delayed second imaginary-part component signal ydi2[n] and the estimated imaginary-part component signal yi′[n] to generate a delayed output imaginary-part component signal eqodi[n]. The second delay 240 is coupled to the first operator 140 for delaying the output real-part component signal eqor[n] to generate a delayed output real-part component signal eqodr[n], wherein the delayed output real-part component signal eqodr[n] and the delayed output imaginary-part component signal eqodi[n] form a delayed complex output signal eqod[n]. In addition, the phase error estimator 250 is coupled to the phase error corrector 130 for estimating the phase error information dr[n] and di[n] according to at least one signal among the detecting result Sd, the output real-part component signal eqor[n], the delayed output real-part component signal eqodr[n], and the delayed output imaginary-part component signal eqodi[n].

In this embodiment, the filter 220 can be a Hilbert Transform circuit or its approximation, but this is not a limitation of the present invention. After the third real-part component signal yr3[n] is processed by the filter 220, an estimated value of the imaginary-part component (i.e., the estimated imaginary-part component signal yi′[n]) will be generated. Due to the characteristics of the Hilbert Transform circuit being well-known to those skilled in the art, and further detailed description is omitted herein for brevity. Furthermore, the second operator 230 can be implemented by an adder. The adder subtracts the estimated imaginary-part component signal yi′[n] from the delayed second imaginary-part component signal ydr2[n], so as to obtain the delayed output imaginary-part component signal eqodi[n] of the equalizer 200. But this is not meant to be a limitation of the present invention, and operators of other types can be adopted to implement the second operator 230.

Please note that the phase error information dr[n] and di[n] constitute a pair of complex signal, which can be expressed by the following equations:
dr[n]=cos Δθ  (1); and
di[n]=sin Δθ  (2).

In complex signal processing, the behavior of the phase error corrector 130 represents a result of rotating the complex signal (yr1[n]+j*yi1[n]) with an angle Δθ, which can be expressed by the following equations:
yr2[n]=yr1[n]*dr[n]−yi1[n]*di[n]  (3); and
yi2[n]=yr1[n]*di[n]+yi1[n]*dr[n]  (4)

As can be known from FIG. 2, since the phase error estimator 250 can estimate the phase error information dr[n] and di[n] according to at least one signal among the detecting result Sd, the output real-part component signal eqor[n], the delayed output real-part component signal eqodr[n], and the delayed output imaginary-part component signal eqodi[n], the phase error of the first real-part component signal yr1[n] and the first imaginary-part component signal yi1[n] can be substantially improved, so as to promote the performance of the equalizer.

Please refer to FIG. 3. FIG. 3 is a flowchart illustrating a method applied to an equalizer according to an exemplary embodiment of the present invention. Please note that the following steps are not limited to be performed according to the exact sequence shown in FIG. 3 if a roughly identical result can be obtained. The method includes, but is not limited to, the following steps:

Step 302: Start.

Step 304: Receive an input real-part component signal of a complex input signal, and equalize the input real-part component signal to generate a first real-part component signal. Go to Step 308.

Step 306: Receive an input imaginary-part component signal of the complex input signal, and equalize the input imaginary-part component signal to generate a first imaginary-part component signal. Go to Step 308.

Step 308: Adjust a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information. Go to Step 310.

Step 310: Perform an operation on the second real-part component signal and a third real-part component signal to generate an output real-part component signal. Go to Step 312.

Step 312: Perform a hard decision on the output real-part component signal to generate a detecting result. Go to Step 314.

Step 314: Equalize the detecting result to generate the third real-part component signal.

How each element operates can be known by collocating the steps shown in FIG. 3 and the elements shown in FIG. 1. Further description of the operations of each step shown in FIG. 3 is omitted here for brevity.

Please refer to FIG. 4. FIG. 4 is a flowchart illustrating a method applied to an equalizer according to another exemplary embodiment of the present invention. The method includes, but is not limited to, the following steps:

Step 302: Start.

Step 304: Receive an input real-part component signal of a complex input signal, and equalize the input real-part component signal to generate a first real-part component signal. Go to Step 308.

Step 306: Receive an input imaginary-part component signal of the complex input signal, and equalize the input imaginary-part component signal to generate a first imaginary-part component signal. Go to Step 308.

Step 308: Adjust a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information. Go to Step 310 and Step 410.

Step 310: Perform an operation on the second real-part component signal and a third real-part component signal to generate an output real-part component signal. Go to Step 312.

Step 312: Perform a hard decision on the output real-part component signal to generate a detecting result. Go to Step 314.

Step 314: Equalize the detecting result to generate the third real-part component signal. Go to Step 420.

Step 410: Delay the second imaginary-part component signal to generate a delayed second imaginary-part component signal. Go to Step 430.

Step 420: Receive the third real-part component signal, and generate the estimated imaginary-part component signal according to the third real-part component signal. Go to Step 430.

Step 430: Perform an operation on the delayed second imaginary-part component signal and the estimated imaginary-part component signal to generate a delayed output imaginary-part component signal. Go to Step 450.

Step 440: Delay the output real-part component signal to generate a delayed output real-part component signal. Go to Step 450.

Step 450: Estimate the phase error information corresponding to the input real-part component signal and the input imaginary-part component signal according to at least one signal among the detecting result, the output real-part component signal, the delayed output real-part component signal, and the delayed output imaginary-part component signal.

The steps shown in FIG. 4 are similar to the steps shown in FIG. 3, as FIG. 4 is a variation of the embodiment shown in FIG. 3. The difference between them is that the operations and functions of the first delay 210, the filter 220, the second operator 230, the second delay 240, and the phase error estimator 250 (i.e., the steps 410˜450) are added into the flowchart of FIG. 4. Therefore, the phase error of the first real-part component signal yr1[n] and the first imaginary-part component signal yi1[n] can be further improved. How each element operates can be known by collocating the steps shown in FIG. 4 and the elements shown in FIG. 2. Further description of the operations of each step shown in FIG. 4 is omitted here for brevity.

Be note that the steps of the flowchart mentioned above are merely a practicable embodiment of the present invention, and should not be considered as limitations of the present invention. The method can include other intermediate steps or can merge several steps into a single step without departing from the spirit of the present invention.

The abovementioned embodiments are presented merely for describing the present invention, and in no way should be considered to be limitations of the scope of the present invention. In summary, the present invention provides an equalizer and a related method. By respectively adopting the first feed-forward equalization module 110 and the second feed-forward equalization module 120 to equalize the input real-part component signal xr[n] and the input imaginary-part component signal xi[n], the signals inputted to the phase error corrector 130 can consist of two-dimensional inputs. Therefore, not only can the efficiency of the phase error corrector 130 for adjusting the phase error be improved, but also can the performance of the equalizer be promoted. Moreover, the output real-part component signal eqor[n] of the equalizer 100 can be obtained by processing the second real-part component signal yr2[n] outputted from the phase error corrector 130 according to its feedback circuits. The estimated imaginary-part component signal yi′[n] can be generated by the filter 220 according to the third real-part component signal yr3[n]. After that, the estimated imaginary-part component signal yi′[n] is subtracted from the delayed second imaginary-part component ydi2[n] by a subtractor, so as to obtain the delayed output imaginary-part component signal eqodi[n]. Finally, the obtained signals (such as the detecting result Sd, the output real-part component signal eqor[n], the delayed output real-part component signal eqodr[n], and the delayed output imaginary-part component signal eqodi[n]) are inputted to the phase error estimator 250 for estimating the phase error information dr[n] and di[n]. Therefore, the phase error of the first real-part component signal yr1[n] and the first imaginary-part component signal yi1[n] can be substantially improved, so as to promote the performance of the equalizer.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims

1. An equalizer, comprising:

a first feed-forward equalization module, for receiving an input real-part component signal of a complex input signal and for equalizing the input real-part component signal to generate a first real-part component signal;
a second feed-forward equalization module, for receiving an input imaginary-part component signal of the complex input signal and for equalizing the input imaginary-part component signal to generate a first imaginary-part component signal; and
a phase error corrector, coupled to an output of the first feed-forward equalization module and an output of the second feed-forward equalization module, for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information and
a first operator, coupled to the phase error corrector, for performing an operation on the second real-part component signal and a third real-part component signal to generate an output real-part component signal;
a slicer, coupled to the first operator, for performing a hard decision on the output real-part component signal to generate a detecting result; and
a feedback equalization module, coupled to the slicer and the first operator, for equalizing the detecting result to generate the third real-part component signal.

2. The equalizer of claim 1, wherein the second feed-forward equalization module equalizes the input imaginary-part component signal according to tap coefficients adopted by the first feed-forward equalization module.

3. The equalizer of claim 1, wherein the complex input signal is a vestigial sideband (VSB) signal.

4. The equalizer of claim 1, wherein the first operator is an adder for subtracting the third real-part component signal from the second real-part component signal to generate the output real-part component signal.

5. The equalizer of claim 1, further comprising:

a first delay, coupled to the phase error corrector, for delaying the second imaginary-part component signal to generate a delayed second imaginary-part component signal;
a filter, coupled to the feedback equalization module, for receiving the third real-part component signal and for generating an estimated imaginary-part component signal according to the third real-part component signal; and
a second operator, coupled to the filter and the first delay, for performing an operation on the delayed second imaginary-part component signal and the estimated imaginary-part component signal to generate a delayed output imaginary-part component signal.

6. The equalizer of claim 5, wherein the second operator is an adder for subtracting the estimated imaginary-part component signal from the delayed second imaginary-part component signal to generate the delayed output imaginary-part component signal.

7. The equalizer of claim 5, further comprising:

a second delay, coupled to the first operator, for delaying the output real-part component signal to generate a delayed output real-part component signal;
wherein the delayed output real-part component signal and the delayed output imaginary-part component signal form a delayed complex output signal.

8. The equalizer of claim 7, further comprising:

a phase error estimator, coupled to the phase error corrector, for estimating the phase error information corresponding to the input real-part component signal and the input imaginary-part component signal according to at least one signal among the detecting result, the output real-part component signal, the delayed output real-part component signal, and the delayed output imaginary-part component signal.

9. The equalizer of claim 1, wherein each of the first feed-forward equalization module and the second feed-forward equalization module is a tapped delay line equalizer.

10. The equalizer of claim 1, being a decision feedback equalizer (DFE).

11. A method applied to an equalizer, comprising:

receiving an input real-part component signal of a complex input signal, and
equalizing the input real-part component signal to generate a first real-part component signal; receiving an input imaginary-part component signal of the complex input signal, and equalizing the input imaginary-part component signal to generate a first imaginary-part component signal; and
adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information; and performing an operation on the second real-part component signal and a third real-part component signal to generate an output real-part component signal;
performing a hard decision on the output real-part component signal to generate a detecting result; and equalizing the detecting result to generate the third real-part component signal.

12. The method of claim 11, wherein the step of equalizing the input real-part component signal comprises:

equalizing the input real-part component signal according to tap coefficients adopted by a first feed-forward equalization module; and
the step of equalizing the input imaginary-part component signal comprises:
equalizing the input imaginary-part component signal according to the tap coefficients adopted by the first feed-forward equalization module.

13. The method of claim 11, wherein the complex input signal is a vestigial sideband (VSB) signal.

14. The method of claim 11, wherein the step of performing the operation on the second real-part component signal and the third real-part component signal to generate the output real-part component signal comprises:

subtracting the third real-part component signal from the second real-part component signal to generate the output real-part component signal.

15. The method of claim 11, further comprising:

delaying the second imaginary-part component signal to generate a delayed second imaginary-part component signal;
receiving the third real-part component signal, and generating an estimated imaginary-part component signal according to the third real-part component signal; and
performing an operation on the delayed second imaginary-part component signal and the estimated imaginary-part component signal to generate a delayed output imaginary-part component signal.

16. The method of claim 15, wherein the step of performing the operation on the delayed second imaginary-part component signal and the estimated imaginary-part component signal to generate the delayed output imaginary-part component signal comprises:

subtracting the estimated imaginary-part component signal from the delayed second imaginary-part component signal to generate the delayed output imaginary-part component signal.

17. The method of claim 15, further comprising:

delaying the output real-part component signal to generate a delayed output real-part component signal;
wherein the delayed output real-part component signal and the delayed output imaginary-part component signal form a delayed complex output signal.

18. The method of claim 17, further comprising:

estimating the phase error information corresponding to the input real-part component signal and the input imaginary-part component signal according to at least one signal among the detecting result, the output real-part component signal, the delayed output real-part component signal, and the delayed output imaginary-part component signal.
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Patent History
Patent number: 8284827
Type: Grant
Filed: Oct 26, 2009
Date of Patent: Oct 9, 2012
Patent Publication Number: 20100111158
Assignee: Realtek Semiconductor Corp. (Hsinchu)
Inventors: Yi-Lin Li (Kao-Hsiung), Cheng-Yi Huang (I-Lan Hsien)
Primary Examiner: David Ometz
Assistant Examiner: Santiago Garcia
Attorney: Thomas, Kayden, Horstemeyer & Risley, LLP
Application Number: 12/605,384
Classifications
Current U.S. Class: Adaptive (375/232); Equalizers (375/229); With Control Of Equalizer And/or Delay Network (333/18)
International Classification: H03K 5/159 (20060101);