Patents by Inventor Yi-Lin Tsai

Yi-Lin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145372
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Wen TSAO, Wen-Chen HSIEH, Yi-Lin TSAI, Hsiu-Fang CHIEN
  • Patent number: 11956261
    Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Acer Cyber Security Incorporated
    Inventors: Chiung-Ying Huang, Yi-Chung Tseng, Ming-Kung Sun, Tung-Lin Tsai
  • Patent number: 11956541
    Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 9, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chen-Hsien Fan, Sung-Mao Tsai, Yueh-Lin Lee, Yu-Chiao Lo, Mao-Kuo Hsu, Ching-Chieh Huan, Yi-Chun Cheng
  • Patent number: 11942467
    Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
  • Publication number: 20240096289
    Abstract: The disclosure provides a control method of a display driver. The control method includes receiving address information and defining an IC address according to the address information. The IC address includes n bits representing k zones, and n and k are positive integers. The control method further includes receiving the IC address, a black frame data signal and a pulse-width modulation (PWM) signal, and turning on or off the plurality of LEDs in the corresponding zone according to toggle of bit in the black frame data signal. Each bit in the black frame data signal indicates that a plurality of LEDs in a zone among the k zones are turned on or off.
    Type: Application
    Filed: February 13, 2023
    Publication date: March 21, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Yi-Yang Tsai, Hung-Ho Huang, Tzong-Honge Shieh, Chieh-An Lin, Po-Hsiang Fang, Jhih-Siou Cheng
  • Patent number: 11935769
    Abstract: The present disclosure provides a chemical supply system, including a chamber, a tubing extending into the chamber, an interlock apparatus, including a fixture for fastening the tubing, and means for determining whether the tubing is fastened by the fixture.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fang-Pin Chiang, Tsung-Lin Tsai, Chaoyen Huang, Yi Chuan Chen
  • Publication number: 20240047427
    Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Applicant: MediaTek Inc.
    Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20240038614
    Abstract: A semiconductor package structure includes a substrate, a dummy conductive mesh structure, an interposer, an underfill material, and a semiconductor die. The substrate includes a wiring structure in dielectric layers. The dummy conductive mesh structure is embedded in the substrate and is spaced apart from the wiring structure by the dielectric layers. The interposer is disposed over the substrate. The underfill material extends between the substrate and the interposer and over the dummy conductive mesh structure. The semiconductor die is disposed over the interposer and is electrically coupled to the wiring structure through the interposer.
    Type: Application
    Filed: June 27, 2023
    Publication date: February 1, 2024
    Inventors: Yi-Lin TSAI, Nai-Wei LIU, Wen-Sung HSU
  • Patent number: 11881142
    Abstract: An image brightness adjusting method, comprising: (a) computing or predicting a first input frame rate according to at least one first input image; (b) generating a first brightness according to a first brightness curve and the first input frame rate, wherein the first brightness curve corresponds to a first frame rate; (c) generating a second brightness according to a second brightness curve and the first input frame rate, wherein the second brightness curve corresponds to a second frame rate; (d) generating a first brightness compensating curve according to the first input frame rate and a brightness difference between the first brightness and the second brightness; and (e) setting a first compensating brightness of at least one second input image according to the first brightness compensating curve.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: January 23, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yi-Chu Li, Chun-Hsing Hsieh, Yi-Lin Tsai
  • Publication number: 20240014143
    Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer, a first semiconductor die, a second semiconductor die, an adhesive layer, and a molding material. The second redistribution layer is disposed over the first redistribution layer. The first semiconductor die and the second semiconductor die are stacked vertically between the first redistribution layer and the second redistribution layer. The first semiconductor die is electrically coupled to the first redistribution layer, and the second semiconductor die is electrically coupled to the second redistribution layer. The adhesive layer extends between the first semiconductor die and the second semiconductor die. The molding material surrounds the first semiconductor die, the adhesive layer, and the second semiconductor die.
    Type: Application
    Filed: June 8, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Lin TSAI, Kun-Ting HUNG, Yin-Fa CHEN, Chi-Yuan CHEN, Wen-Sung HSU
  • Patent number: 11854930
    Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: December 26, 2023
    Assignee: MediaTek Inc.
    Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
  • Publication number: 20230387075
    Abstract: A semiconductor package includes an interposer over a substrate that includes interconnect traces, a redistribution structure on the interposer, a first semiconductor structure, a second semiconductor structure and a third semiconductor structure on the redistribution structure. The first semiconductor structure includes a first semiconductor die and a first encapsulant that encapsulates the first semiconductor die. The second semiconductor structure includes a second semiconductor die and a second encapsulant that encapsulates the second semiconductor die. The third semiconductor structure is disposed adjacent to a corner or an edge of the substrate in a top plan view of the substrate. The third semiconductor structure includes a third semiconductor die and a third encapsulant that encapsulates the third semiconductor die. The third semiconductor structure is electrically insulated from the substrate, the first semiconductor structure and the second semiconductor structure.
    Type: Application
    Filed: April 20, 2023
    Publication date: November 30, 2023
    Inventors: Yi-Lin TSAI, Wen-Sung HSU, Nai-Wei LIU
  • Patent number: 11830851
    Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 28, 2023
    Assignee: MediaTek Inc.
    Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20230350287
    Abstract: An imprint method includes the following steps. A first resist layer is formed on a first substrate. A first imprinting step using a first mold is performed to the first resist layer. A first etching process is performed to the first substrate with the first resist layer as an etching mask after the first imprinting step so as to form a first recess pattern in the first substrate. A second resist layer is formed on the first substrate. A second imprinting step using a second mold is performed to the second resist layer. A second etching process is performed to the first substrate with the second resist layer as an etching mask after the second imprinting step so as to form second recess patterns in the first substrate. A depth of the first recess pattern is greater than a depth of each of the second recess patterns.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 2, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Su-Yun Fang, Chih-Hsien Tang, Yi-Lin Tsai
  • Publication number: 20230343692
    Abstract: An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 26, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wen-Chen Hsieh, Ya-Ting Chi, Chia-Wen Tsao, Hsin-Yin Chang, Yi-Lin Tsai, Hsiu-Fang Chien
  • Publication number: 20230253342
    Abstract: An electronic package is provided and includes a substrate structure and an electronic element disposed on the substrate structure. The substrate structure is provided with a plurality of circuits and a reinforcing portion that is free from being electrically connected to the plurality of circuits on a surface of a substrate body of the substrate structure, such that the electronic element is electrically connected to the plurality of circuits and is free from being electrically connected to the reinforcing portion, and the reinforcing portion includes a dummy pad and a trace line connected to the dummy pad to increase a layout area of the reinforcing portion on the substrate body. Therefore, the adhesion of the reinforcing portion can be improved, and the electronic element can be prevented from cracking.
    Type: Application
    Filed: August 23, 2022
    Publication date: August 10, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hsiu-Fang Chien, Wen-Chen Hsieh, Chia-Wen Tsao, Hsin-Yin Chang, Ya-Ting Chi, Yi-Lin Tsai
  • Patent number: 11670596
    Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: June 6, 2023
    Assignee: MEDIATEK INC.
    Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20230060065
    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The two-part lid comprises an annular lid base and a cover plate removably installed on the annular lid base.
    Type: Application
    Filed: July 25, 2022
    Publication date: February 23, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yi-Lin Tsai, Yi-Jou Lin, Tsai-Ming Lai, Wei-Chen Chang
  • Publication number: 20230005808
    Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
    Type: Application
    Filed: September 1, 2022
    Publication date: January 5, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
  • Patent number: 11499244
    Abstract: Disclosed is a device for impregnation using electrophoresis, which includes a chassis, a storing unit, a pipeline unit, an injection unit, a bearing tank, a first driver element and a second driver element, wherein the storing unit has several storage tanks storing the materials for impregnation. The pipeline unit has several pipelines connecting the storage tanks and the injection unit. The injection unit has a static mixing tube and an injector, so as to inject said materials for impregnation into the several slide sets located in the bearing tank. The first driver element drives the bearing tank to reciprocate transversely, and the second driver element drives the injection unit to shift up and down. The device can perform impregnation operations automatically, with quick operation and low operational difficulty level, while the prepared gel has high quality stability and yield.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 15, 2022
    Inventors: De-Li Chiu, Yi-Lin Tsai, Fan-Pin Yen