Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: The present invention discloses a combinational therapy for enhancing efficacy of immune checkpoint blockade for tumors with immune suppressive microenvironment. More specifically, this combination therapy involves the treatment of cancer through immune checkpoint inhibitors and CpG-oligodeoxynucleotides.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: The present invention discloses a combinational therapy for enhancing efficacy of immune checkpoint blockade for tumors with immune suppressive microenvironment. More specifically, this combination therapy involves the treatment of cancer through immune checkpoint inhibitors and CpG-oligodeoxynucleotides.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.

Abstract: A patient support structure includes a first supporting part, a second supporting part and a third supporting part. The first supporting part includes a first resilient member; the second supporting part includes a second resilient member; and the third supporting part is between the first supporting part and the second supporting part. The first supporting part, the second supporting part and the third supporting part together define a supporting surface extending along a longitudinal axis, and the second resilient member includes a first supporting area and a second supporting area different in supporting strength.

Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.

Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.

Abstract: A CpG-oligodeoxynucleotide (CpG-ODN) for inducing a TLR9 activated immune response, a TLR21 activated immune response or a combination thereof in a host is provided. The CpG-ODN includes one or more copies of the sequences of GTCGTT, one or more copies of the sequences of GTT and one or more copies of the sequences of TTTT, wherein at least one copy of the sequence of GTCGTT is encoded between the sequence of GTT and the sequence of TTTT. Further, an immunogenic composition including the CpG-ODN and a method of inducing immune response by the same are also provided.

Abstract: A CpG-oligodeoxynucleotide (CpG-ODN) for inducing a TLR9 activated immune response, a TLR21 activated immune response or a combination thereof in a host is provided. The CpG-ODN includes one or more copies of the sequences of GTCGTT, one or more copies of the sequences of GTT and one or more copies of the sequences of TTTT, wherein at least one copy of the sequence of GTCGTT is encoded between the sequence of GTT and the sequence of TTTT. Further, an immunogenic composition including the CpG-ODN and a method of inducing immune response by the same are also provided.

Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.

Abstract: A patient support structure comprises a first supporting part, a second supporting part and a third supporting part. The first supporting part comprises a first resilient member; the second supporting part comprises a second resilient member; and the third supporting part is between the first supporting part and the second supporting part. The first supporting part, the second supporting part and the third supporting part together define a supporting surface extending along a longitudinal axis, and the second resilient member comprises a first supporting area and a second supporting area different in supporting strength.

Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area on a surface of a substrate during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device, wherein at least one electrical device is provided on the surface of the substrate and the at least one electrical device includes a temperature sensor. The acoustic wave device protection structure comprising: a metal covering layer, having a concave surface and a bottom rim, the bottom rim connected to the acoustic wave device and forming at least one opening between the bottom rim and the acoustic wave device, and the concave surface covering over the resonant area to form a cavity between the concave surface and the resonant area.