Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: The present application provides an operation device and related products. The operation device is configured to execute operations of a network model, wherein the network model includes a neural network model and/or non-neural network model; the operation device comprises an operation unit, a controller unit and a storage unit, wherein the storage unit includes a data input unit, a storage medium and a scalar data storage unit. The technical solution provided by this application has advantages of a fast calculation speed and energy-saving.

Abstract: A magnetoresistive element comprises a nonmagnetic nano-current-channel (NCC) structure provided on a surface of the magnetic recording layer, which is opposite to a surface of the magnetic recording layer where the tunnel barrier layer is provided, and comprising a spatial distribution of perpendicular conducting channels throughout the NCC structure thickness and surrounded by an insulating medium, making the magnetic recording layer a magnetically soft-hard composite structure. Correspondingly, the critical write current and write power are reduced with reversal modes of exchange-spring magnets of the magnetically soft-hard composite structure.

Abstract: The present disclosure relates to a device and a system for testing flatness. The device for testing flatness includes a base, a testing platform, and a ranging sensor. The testing platform is assembled on the base. The testing platform includes a supporting structure. The supporting structure is disposed on the side of the testing platform away from the base and is used to support a to-be-tested board. The structure matches the structure of the to-be-tested board. The ranging sensor is disposed on the side of the testing platform away from the base. After the to-be-tested board is placed on the testing platform, the ranging sensor is used to test distances between a number N of to-be-tested positions on the to-be-tested board and the ranging sensor, to obtain N pieces of distance information, and the N pieces of distance information are used to determine the flatness of the to-be-tested board, where N is an integer greater than 2.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: A method and composition for doped HTS tapes having directional flux pinning and critical current.

Abstract: An anti-peeping backlight module is formed by stacking an upper backlight module, a lower backlight module and a reflecting film disposed below the lower backlight module, wherein the upper backlight module is a transparent module, the lower backlight module is a transparent module or a non-transparent module, the upper backlight module is a collimating backlight module or a diffusion backlight module, the lower backlight module is a collimating backlight module or a diffusion backlight module, and the upper backlight module and the lower backlight module have different properties. The anti-peeping backlight module realizes beam splitting and collimation and can be used as various backlight modules, the beam splitting angle is adjustable, the efficiency is high, and can be controlled independently.

Abstract: A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.

Abstract: A flyback converter is provided that detects a load-transient-produced increase in the output current to more quickly detect and respond to the load transient.

Abstract: Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.

Abstract: A flyback converter is provided that dynamically adjusts a drain threshold voltage for a current cycle of a synchronous rectifier switch transistor based upon operating conditions in a previous cycle of the synchronous rectifier switch transistor. A differential amplifier drives a gate voltage of the synchronous rectifier switch transistor during an on-time of the current cycle so that a drain voltage of the synchronous rectifier switch transistor equals the drain threshold voltage during a regulated portion of the current cycle.

Abstract: A system for authenticating a user attempting to access a computing device or a software application executing thereon. A data storage device stores one or more digital images or frames of video of face(s) of authorized user(s) of the device. The system subsequently receives from a first video camera one or more digital images or frames of video of a face of the user attempting to access the device and compares the image of the face of the user attempting to access the device with the stored image of the face of the authorized user of the device. To ensure the received video of the face of the user attempting to access the device is a real-time video of that user, and not a forgery, the system further receives a first photoplethysmogram (PPG) obtained from a first body part (e.g., a face) of the user attempting to access the device, receives a second PPG obtained from a second body part (e.g., a fingertip) of the user attempting to access the device, and compares the first PPG with the second PPG.

Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: Disclosed are a temperature measurement circuit and method. The circuit includes a first temperature sensing circuit, a second temperature sensing circuit and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for characterizing a temperature based on an inputted first current signal, a magnitude of the first current signal being correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for characterizing the temperature based on an inputted second current signal, the second current signal being independent of temperature. The data processing unit is configured to determine a current temperature based on a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal.

Abstract: A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.

Abstract: A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.

Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

Abstract: A distribution method includes: distributing, when multiple feature maps exist in an image processing model, to each feature map a neuron through which the feature map passes; filtrating, according to importance of neurons of multiple convolution layers in an image processing model, the neurons to obtain a first result; collecting, according to a position attribute of the each neuron in the first result, statistics on a scale of the feature map corresponding to each neuron to obtain a distribution relationship; the distribution relationship indicates a correspondence between the each feature map and the neuron through which the feature map passes; and distributing, according to the distribution relationship, to the each feature map the neuron through which the feature map passes.

Abstract: The present disclosure relates to a device and a system for testing flatness. The device for testing flatness includes a base, a testing platform, and a ranging sensor. The testing platform is assembled on the base. The testing platform includes a supporting structure. The supporting structure is disposed on the side of the testing platform away from the base and is used to support a to-be-tested board. The structure matches the structure of the to-be-tested board. The ranging sensor is disposed on the side of the testing platform away from the base. After the to-be-tested board is placed on the testing platform, the ranging sensor is used to test distances between a number N of to-be-tested positions on the to-be-tested board and the ranging sensor, to obtain N pieces of distance information, and the N pieces of distance information are used to determine the flatness of the to-be-tested board, where N is an integer greater than 2.