Patents by Inventor Yi-Min Fu

Yi-Min Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282586
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: May 10, 2022
    Publication date: September 7, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
  • Publication number: 20230253331
    Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.
    Type: Application
    Filed: August 29, 2022
    Publication date: August 10, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Chao-Chiang Pu, Yu-Po Wang
  • Publication number: 20230154865
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 18, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Publication number: 20230111192
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: November 16, 2021
    Publication date: April 13, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
  • Publication number: 20220399246
    Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 15, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Yu-Po Wang
  • Patent number: 10396021
    Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 27, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen
  • Publication number: 20180233442
    Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen
  • Patent number: 9972564
    Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 15, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen
  • Publication number: 20150206814
    Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
    Type: Application
    Filed: May 29, 2014
    Publication date: July 23, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen