Abstract: A torque module, a rotating shaft assembly, and an electronic device. The torque module includes a rotating shaft, a first blocking member, a second blocking member, a rotating assembly, a sliding assembly, and a first elastic member. The rotating assembly is sleeved on the rotating shaft and disposed between the first blocking member and the second blocking member, and the rotating assembly is arranged with a first mating portion. The sliding assembly includes a first sliding member sleeved on the rotating shaft, and the first sliding member is arranged with a second mating portion. The first elastic member is sleeved on the rotating shaft and disposed between the rotating assembly and the second blocking member. When the sliding assembly slides away from the rotating assembly, the first elastic member is compressed and the rotating assembly remains stationary relative to the sliding assembly when the rotating assembly stops rotating.

Abstract: An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

Abstract: Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

Abstract: There is provided a display substrate, including: a base; light-emitting units on a side of the base; a flat light-shielding functional layer, including a black matrix and a first planarization layer, on a side of the light-emitting units away from the base, light outgoing openings being provided in the black matrix and being in one-to-one correspondence with the light-emitting units, and the first planarization layer at least filling the light outgoing openings; and a color filter layer, including color filter patterns in one-to-one correspondence with the light outgoing openings, on a side of the flat light-shielding functional layer away from the base, an orthographic projection of each color filter pattern on the base covering an orthographic projection of the light outgoing opening corresponding to the color filter pattern on the base. A method for manufacturing a display substrate, a display panel and a display apparatus are further provided.

Abstract: A method, device, system, and storage medium for tracking a moving target are provided. The method uses three-dimensional radar observation data to construct a state vector and a motion model of the moving target, thereby to construct a state equation and an observation equation for achieving filtering and tracking within a linear Gaussian framework. The disclosure is also suitable for a moving target in a two-dimensional scene with a distance and an azimuth, and the disclosure use a two-dimensional observation vector to construct a dynamic system to achieving tracking of the moving target. The disclosure can be used in radar systems containing Doppler measurements, and tracking of moving targets can be implemented by performing dimension-expansion processing on observation equations.

Abstract: The present specification relates to the field of data processing, and in particular, to a storage method for graph data and a distributed computing method for graph data. The graph data includes nodes and edges, the nodes include entity nodes and non-entity nodes, and the storage method for the graph data includes: obtaining a first table and a second table based on the graph data; obtaining first sub-tables and second sub-tables respectively corresponding to a plurality of entity node groups; and distributing the first sub-tables and the second sub-tables corresponding to the entity node groups to a plurality of computing units for distributed storage. In the distributed computing method for the graph data, the graph data is stored in a plurality of computing units in a distributed way according to the storage method for the graph data, and the method can be executed by one of the computing units.

Abstract: Systems or methods of the present disclosure may provide a compilation design method that uses cloud computing resources and/or distributed computing resources to compile initial user designs. The initial user design for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic. The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs.

Abstract: The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and/or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

Abstract: The present disclosure provides a method and an apparatus for user equipment (UE) registering, an electronic device and a storage medium. Under 5G core network slice isolation networking, when an AMF network element detects that a UE is unsuccessfully registered on the AMF network element, the AMF network element sends to the UE a registration reject message comprising at least a first cell and a second cell. In this way, when the UE sends registration information again, the UE can select target network slice information based on network slice information configured in the first cell. And a 5G base station, when receiving the registration information from the UE, determines a corresponding target AMF network element based on the target network slice information in the requested NSSAI, such that the UE can be successfully registered to the target AMF network element.

Abstract: A combination comprises two propylene-based polymers which can provide flexibility in adjusting shrinkage rate of components comprising such combination.

Abstract: Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: Provided are a speech recognition method, a speech recognition apparatus, a computer readable storage medium, and an electronic device. The method comprises: obtaining a sample speech signal, decoding the sample speech signal, obtaining a decoding result, and extracting a first feature from the decoding result; extracting a target speech segment from the sample speech signal, obtaining a log magnitude spectrum of the target speech segment, and determining a second feature according to the log magnitude spectrum; combining the first feature and the second feature to obtain a third feature; training an untrained classifier by using the third feature so as to obtain a trained classifier; and obtaining a third feature to be recognized of a speech signal to be recognized, so as to determine whether the third feature to be recognized comprises a prepositive word.

Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: The disclosure relates to the technical field of autonomous driving, and specifically provides a point cloud object detection method, a computer device, a storage medium, and a vehicle, to solve the problem of improving the accuracy of point cloud object detection. The method includes: obtaining a three-dimensional (3D) point cloud frame collected by a radar, performing object detection on the 3D point cloud frame to obtain a 3D object bounding box represented by 3D coordinates of bounding box corner points, and obtaining an object detection result based on the 3D object bounding box. Through the method, even if an object is covered, coordinates of uncovered end points of the object can be accurately obtained based on 3D coordinates of bounding box corner points in a 3D object bounding box, so that the accuracy of object detection can be effectively improved, and effective tracking corner points are provided for object tracking, thereby ensuring the accuracy and reliability of object tracking.

Abstract: An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.

Abstract: The invention discloses a preparation method for a vanadium-nitrogen alloy, which comprises the following steps: a, adding ammonium vanadate into a first rotary kiln for heating and deamination to obtain a thermal vanadium oxide and a mixed gas 1; b, adding the thermal vanadium oxide into a second rotary kiln, for heating and reducing in a first protective atmosphere to obtain a vanadium oxynitride and a mixed gas 2; c, mixing a graphite powder and the vanadium oxynitride in a ratio of K:1 by mass percentage to form a mixture, and mixing and molding the mixture to obtain a dried raw meal block, wherein the vanadium oxynitride has an oxygen content of 4%-20%, and the oxygen content is divided into n intervals, and the K value is in direct proportion to the oxygen content in each interval; and d, sending the dried raw material block into a calcining kiln for carbothermal reduction and nitridation in a second protective atmosphere to obtain a vanadium-nitrogen alloy and a mixed gas 3.

Abstract: To mitigate voltage droop while reducing the power and space consumed on the board and reducing switching activity, a clock skipping scheme may be implemented for an FPGA. The clock skipping scheme may be implemented in the FPGA design via an Electronic Design Automation (EDA) tool. The EDA tool may define clock skipping cycles based on customer needs for current ramp up speed (e.g., for an inrush current or an operating current) and clock frequency. The EDA tool may adjust clock skipping based on a power target and/or usage conditions of a user software design. In addition to mitigating voltage droop and reducing space consumed on the board and power consumed by the FPGA, the clock skipping scheme may maintain a base clock frequency, enable timing closure at the base clock frequency, and alleviate the need to reclose timing during clock skipping operations.