Patents by Inventor Yi Peng
Yi Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250148184Abstract: A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.Type: ApplicationFiled: November 6, 2023Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Shun Chen, Tzu-Ching Lin, Shu-Chin Tai, Amit Kundu, Yung-Chow Peng, Hung-Hsiang Lin, Yi-Peng Weng, Chung-Ting Lu
-
Publication number: 20250151335Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.Type: ApplicationFiled: March 8, 2024Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shiang HUANG, Cheng-Yi PENG, Yen-Ting CHEN
-
Publication number: 20250107513Abstract: In a method for counting embryos developing in a uterus of Caenorhabditis elegans, a complete set of experimental procedures are designed to count embryos in the uterus of Caenorhabditis elegans by using Caenorhabditis elegans as a model organism. The method is applicable to Caenorhabditis elegans exposed from an L1 stage to a final stage of pregnancy, and can provide an easy-to-observe, fast, simple, accurate and reliable experimental method to apply Caenorhabditis elegans to research of reproductive ability, detection results of which are highly accurate and reliable, and the experimental method is suitable for promotion.Type: ApplicationFiled: December 9, 2024Publication date: April 3, 2025Applicant: Shanghai UniversityInventors: Hui LI, Chen WANG, Xiaoli WANG, Chongli SHI, Yeyong LI, Lingjun ZENG, Yi PENG
-
Publication number: 20250076597Abstract: An optical communication device includes a dispersion unit and a switching unit that are disposed in a cavity of a closed housing. The optical communication device further includes a monitoring unit and a drive unit. The monitoring unit may monitor in real time offsets of light spots formed on the switching unit. The drive unit can drive the switching unit based on a variation obtained by the monitoring unit, so that the switching unit compensates for the offsets of the light spots. In addition, the optical communication device may further include a dustproof and waterproof unit and a humidity control unit.Type: ApplicationFiled: November 20, 2024Publication date: March 6, 2025Inventors: Mingran Quan, Xinhua Xiao, Junying Zhao, Wei Jia, Heliang Liu, Mengrou Xia, Yi Peng
-
Publication number: 20250062694Abstract: A driving circuit is provided. The driving circuit includes a first switch, a second switch, a temperature sensing circuit, and a control circuit. The first terminal of the first switch is configured to receive an input voltage. The first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is coupled to a ground. The temperature sensing circuit is configured to sense a temperature indicating signal. The control circuit is configured to receive a PWM control signal and the temperature indicating signal and provide an adjusted PWM control signal according to the PWM control signal and the temperature indicating signal. An on-time of the adjusted PWM control signal is different from an on-time of the PWM control signal.Type: ApplicationFiled: August 15, 2024Publication date: February 20, 2025Inventors: Yi-Peng Lin, Shih-An Wang
-
Patent number: 12218203Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.Type: GrantFiled: July 27, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
-
Publication number: 20250040183Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surfacType: ApplicationFiled: July 28, 2023Publication date: January 30, 2025Inventors: Chih-Hao CHANG, Wei-Yang LEE, Kuan-Hao CHENG, Cheng-Yi PENG
-
Publication number: 20250037374Abstract: A computing device obtains an image depicting a watch and performs segmentation on the watch in the image to generate a segmented watch region comprising a watch case region, a first watch strap region, and a second watch strap region. The computing device generates a three-dimensional (3D) mesh according to the watch case region, the first watch strap region, the second watch strap region, and a pre-defined skeleton containing at least one straight part and at least two curved parts. The computing device generates texture attributes according to the segmented watch and applies the texture attributes to the 3D mesh to generate a textured 3D watch object. The computing device renders the textured 3D watch object in an augmented reality display.Type: ApplicationFiled: July 19, 2024Publication date: January 30, 2025Inventors: Hsin-Yi PENG, Chih-Yu CHENG
-
Publication number: 20250004892Abstract: An apparatus and method for redundant data processing with graceful degrading functionality. For example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements are to operate in a second redundancy mode excluding the one processing element.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Inventors: Brandon GORDON, Yi PENG, krishna NAGAR, Nathan KRUEGER
-
Publication number: 20240379814Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
-
Patent number: 12142663Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: GrantFiled: July 24, 2023Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
-
Publication number: 20240370064Abstract: A torque module, a rotating shaft assembly, and an electronic device. The torque module includes a rotating shaft, a first blocking member, a second blocking member, a rotating assembly, a sliding assembly, and a first elastic member. The rotating assembly is sleeved on the rotating shaft and disposed between the first blocking member and the second blocking member, and the rotating assembly is arranged with a first mating portion. The sliding assembly includes a first sliding member sleeved on the rotating shaft, and the first sliding member is arranged with a second mating portion. The first elastic member is sleeved on the rotating shaft and disposed between the rotating assembly and the second blocking member. When the sliding assembly slides away from the rotating assembly, the first elastic member is compressed and the rotating assembly remains stationary relative to the sliding assembly when the rotating assembly stops rotating.Type: ApplicationFiled: June 28, 2024Publication date: November 7, 2024Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.Inventors: Yaxing XU, Changchun SHI, Yi PENG, Hongdong HUANG, Qiuliang CHEN, Zihao LIANG
-
Publication number: 20240371970Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.Type: ApplicationFiled: July 14, 2024Publication date: November 7, 2024Inventors: Chun Hsiung TSAI, Cheng-Yi PENG, Yin-Pin WANG, Kuo-Feng YU, Da-Wen LIN, Jian-Hao CHEN, Shahaji B. MORE
-
Patent number: 12135332Abstract: One aspect of the present disclosure relates to an isolated mutant human estrogen receptor alpha (hER?) that may be used in methods of drug discovery. The isolated mutant hER? can include a DNA-binding domain (DBD), a ligand-binding domain (LBD), and an interface between the DBD and the LBD, wherein at least one tryptophan residue is mutated to a phenylalanine residue.Type: GrantFiled: November 26, 2019Date of Patent: November 5, 2024Assignee: CASE WESTERN RESERVE UNIVERSITYInventors: Sichun Yang, Yi Peng
-
Patent number: 12129561Abstract: A catalyst nanocomposite and methods of making the same. The catalyst nanocomposite includes a substrate; and a coating disposed on the substrate, the coating having a ruthenium and nitrogen co-doped carbon matrix. The coating may be melamine and formaldehyde and produced via pyrolizing the melamine and formaldehyde on a nanowire made of metals such as tellurium.Type: GrantFiled: September 27, 2019Date of Patent: October 29, 2024Assignee: The Regents of the University of CaliforniaInventors: Shaowei Chen, Bingzhang Lu, Lin Guo, Yi Peng, Jia-En Lu
-
Patent number: 12105097Abstract: The present invention relates to a peptide capable of binding to rheumatoid arthritis autoantibodies, which is a consecutive 10-25 amino acid sequence of any one fragment of the group consisting of SEQ ID NO: 3-4, 7-13 or 16-19, wherein the peptide fragment has an epitope that binds to the rheumatoid arthritis autoantibodies. Furthermore, the peptide fragment bound to the rheumatoid arthritis autoantibodies is used for testing rheumatoid arthritis, and according to this use, the present invention provides a method for testing rheumatoid arthritis disease and a test reagent kit used for determining whether a subject to be tested suffers from rheumatoid arthritis disease.Type: GrantFiled: January 20, 2020Date of Patent: October 1, 2024Assignee: CHINA MEDICAL UNIVERSITYInventors: Gregory Tsay, Hsin-Yi Peng
-
Publication number: 20240322011Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.Type: ApplicationFiled: June 7, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi PENG, Wen-Yuan CHEN, Wen-Hsing HSIEH, Yi-Ju HSU, Jon-Hsu HO, Song-Bor LEE, Bor-Zen TIEN
-
Publication number: 20240303406Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.Type: ApplicationFiled: May 15, 2024Publication date: September 12, 2024Inventors: Yi Peng, Brandon Lewis Gordon
-
Patent number: 12086460Abstract: Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.Type: GrantFiled: December 23, 2020Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Bee Yee Ng, Jun Pin Tan, Yi Peng
-
Patent number: 12075005Abstract: In a voice signal relay and transfer method for a voice call between a radio voice terminal and a remote device includes, a radio voice signal is received from the radio voice terminal and converting the radio voice signal into a digital voice signal. The digital voice signal is further converted into a group of voice packets in a streaming form. Then the group of voice packets is transmitted to a streaming server via a mobile communication network. The group of voice packets is further transferred from the streaming server to the remote device in a streaming form.Type: GrantFiled: December 7, 2020Date of Patent: August 27, 2024Assignee: ALPHA NETWORKS INC.Inventors: Shih Chieh Su, Ching-Chung Chiang, Yi Peng Cheng