Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: Various embodiments of the teachings herein include an interface mapping method. An example includes: converting an open application programming interface (API) description file of a microservice to a first communication standard interface description file; and mapping multiple parameter names in a functional interface in the first communication standard interface description file into a functional block corresponding to the functional interface.

Abstract: Various embodiments of the teachings herein include a workflow creation method. Some examples include: receiving an operation performed by a user on a GUI constructing a functional block model; receiving an operation performed by the user including nesting a behavior tree into a second functional block, wherein the behavior tree defines an operation for a first workcell, and the functional block model defines an operation for a second workcell; in response to a first functional block in the functional block model triggering an input event of the second functional block, then the second functional block triggers an execution signal to a root node in the behavior tree at a preset frequency, so the behavior tree starts execution from the root node and outputs an execution result; the second functional block triggers a corresponding output event according to the execution result; and generating an instance of the functional block model.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media for speech recognition. One method includes obtaining an input acoustic sequence, the input acoustic sequence representing one or more utterances; processing the input acoustic sequence using a speech recognition model to generate a transcription of the input acoustic sequence, wherein the speech recognition model comprises a domain-specific language model; and providing the generated transcription of the input acoustic sequence as input to a domain-specific predictive model to generate structured text content that is derived from the transcription of the input acoustic sequence.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.

Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

Abstract: In a method for counting embryos developing in a uterus of Caenorhabditis elegans, a complete set of experimental procedures are designed to count embryos in the uterus of Caenorhabditis elegans by using Caenorhabditis elegans as a model organism. The method is applicable to Caenorhabditis elegans exposed from an L1 stage to a final stage of pregnancy, and can provide an easy-to-observe, fast, simple, accurate and reliable experimental method to apply Caenorhabditis elegans to research of reproductive ability, detection results of which are highly accurate and reliable, and the experimental method is suitable for promotion.

Abstract: An optical communication device includes a dispersion unit and a switching unit that are disposed in a cavity of a closed housing. The optical communication device further includes a monitoring unit and a drive unit. The monitoring unit may monitor in real time offsets of light spots formed on the switching unit. The drive unit can drive the switching unit based on a variation obtained by the monitoring unit, so that the switching unit compensates for the offsets of the light spots. In addition, the optical communication device may further include a dustproof and waterproof unit and a humidity control unit.

Abstract: A driving circuit is provided. The driving circuit includes a first switch, a second switch, a temperature sensing circuit, and a control circuit. The first terminal of the first switch is configured to receive an input voltage. The first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is coupled to a ground. The temperature sensing circuit is configured to sense a temperature indicating signal. The control circuit is configured to receive a PWM control signal and the temperature indicating signal and provide an adjusted PWM control signal according to the PWM control signal and the temperature indicating signal. An on-time of the adjusted PWM control signal is different from an on-time of the PWM control signal.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A computing device obtains an image depicting a watch and performs segmentation on the watch in the image to generate a segmented watch region comprising a watch case region, a first watch strap region, and a second watch strap region. The computing device generates a three-dimensional (3D) mesh according to the watch case region, the first watch strap region, the second watch strap region, and a pre-defined skeleton containing at least one straight part and at least two curved parts. The computing device generates texture attributes according to the segmented watch and applies the texture attributes to the 3D mesh to generate a textured 3D watch object. The computing device renders the textured 3D watch object in an augmented reality display.

Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surfac

Abstract: An apparatus and method for redundant data processing with graceful degrading functionality. For example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements are to operate in a second redundancy mode excluding the one processing element.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Abstract: A torque module, a rotating shaft assembly, and an electronic device. The torque module includes a rotating shaft, a first blocking member, a second blocking member, a rotating assembly, a sliding assembly, and a first elastic member. The rotating assembly is sleeved on the rotating shaft and disposed between the first blocking member and the second blocking member, and the rotating assembly is arranged with a first mating portion. The sliding assembly includes a first sliding member sleeved on the rotating shaft, and the first sliding member is arranged with a second mating portion. The first elastic member is sleeved on the rotating shaft and disposed between the rotating assembly and the second blocking member. When the sliding assembly slides away from the rotating assembly, the first elastic member is compressed and the rotating assembly remains stationary relative to the sliding assembly when the rotating assembly stops rotating.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: One aspect of the present disclosure relates to an isolated mutant human estrogen receptor alpha (hER?) that may be used in methods of drug discovery. The isolated mutant hER? can include a DNA-binding domain (DBD), a ligand-binding domain (LBD), and an interface between the DBD and the LBD, wherein at least one tryptophan residue is mutated to a phenylalanine residue.

Abstract: A catalyst nanocomposite and methods of making the same. The catalyst nanocomposite includes a substrate; and a coating disposed on the substrate, the coating having a ruthenium and nitrogen co-doped carbon matrix. The coating may be melamine and formaldehyde and produced via pyrolizing the melamine and formaldehyde on a nanowire made of metals such as tellurium.