Abstract: A fusion protein is disclosed. The fusion protein of the invention comprises an Fc fragment of an immunoglobulin G and a bioactive molecule, wherein the Fc is a single chain Fc. The amino acids in the hinge of the Fc is mutated, substituted, or deleted so that the hinge of Fc cannot form disulfide bonds. Methods for producing and using the fusion protein of the invention are also provided.

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: Systems and methods may provide recommendations for a circuit design based on components of the circuit and machine-learning techniques. For example, a system may include a processor-based device storing or accessing a computer-aided design application for an integrated circuit, where the computer-aided design application, when executed by the processor-based device, causes acts to be performed including receiving an indication of a first selected component from a library for a design for the integrated circuit, retrieving one or more suggested components from the library based at least in part on the first selected component, and populating a user interface with the first selected component and a first suggested component of the one or more suggested components for display on the processor-based device.

Abstract: The present disclosure provides an optical device including a tray with a step structure, first filters, second filters, and an optical signal router. The step structure has a first portion and a second portion laterally connected to the first portion. The first portion has a first bottom surface and a first top surface. The second portion has a second bottom surface and a second top surface. The first bottom surface and the second bottom surface are substantially coplanar, and the first portion is thinner than the second portion. The first filters are mounted on the first top surface. The second filters are mounted on the second top surface. The optical signal router optically couples to the first filters and the second filters, and is configured to receive a light beam, transmissible to the tray, from one of the first filters or the second filters.

Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: Example configuration methods and apparatus are described. An example communications system includes a master node and a secondary node that jointly provide a service for a terminal. One example method includes generating configuration information for a signaling radio bearer (SRB) by the secondary node, where the SRB is used to transmit a radio resource control (RRC) message between the secondary node and the terminal. The secondary node sends the configuration information for the SRB to the master node, so that the configuration information for the SRB is sent to the terminal through the master node. The secondary node receives a result of configuring the SRB by the terminal by using the configuration information for the SRB. In this way, the SRB can be established on the secondary node, and used for RRC message transmission between the secondary node and the terminal.

Abstract: An electrical connector assembly includes: a male connector, provided with a conductive shell; a first substrate, accommodated in the conductive shell and used to transmit receiving signals; a second substrate, accommodated in the conductive shell and used to transmit sending signals; a shielding sheet, located between the first substrate and the second substrate; a female connector, provided with a first conductive body and a second conductive body; a plurality of first signal terminals, accommodated in the first conductive body and used to transmit receiving signals; and a plurality of second signal terminals, accommodated in the second conductive body and used to transmit sending signals. The first signal terminals and the first substrate are electrically contacted to each other. The second signal terminals and the second substrate are electrically contacted to each other. The first conductive body and/or the second conductive body are used to lap joint with the shielding sheet.

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Abstract: A method, device, system, and storage medium for tracking a moving target are provided. The method uses three-dimensional radar observation data to construct a state vector and a motion model of the moving target, thereby to construct a state equation and an observation equation for achieving filtering and tracking within a linear Gaussian framework. The disclosure is also suitable for a moving target in a two-dimensional scene with a distance and an azimuth, and the disclosure use a two-dimensional observation vector to construct a dynamic system to achieving tracking of the moving target. The disclosure can be used in radar systems containing Doppler measurements, and tracking of moving targets can be implemented by performing dimension-expansion processing on observation equations.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for jointly training an image embedding model and a text embedding model. In one aspect, a method comprises: processing data from a historical query log of a search system to generate a candidate set of training examples, wherein each training example comprises: (i) a search query comprising a sequence of one or more words, (ii) an image, and (iii) selection data characterizing how often users selected the image in response to the image being identified by a search result for the search query; selecting a plurality of training examples from the candidate set of training examples; and using the training data to jointly train the image embedding model and the text embedding model.