Abstract: Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: Provided are a speech recognition method, a speech recognition apparatus, a computer readable storage medium, and an electronic device. The method comprises: obtaining a sample speech signal, decoding the sample speech signal, obtaining a decoding result, and extracting a first feature from the decoding result; extracting a target speech segment from the sample speech signal, obtaining a log magnitude spectrum of the target speech segment, and determining a second feature according to the log magnitude spectrum; combining the first feature and the second feature to obtain a third feature; training an untrained classifier by using the third feature so as to obtain a trained classifier; and obtaining a third feature to be recognized of a speech signal to be recognized, so as to determine whether the third feature to be recognized comprises a prepositive word.

Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: The disclosure relates to the technical field of autonomous driving, and specifically provides a point cloud object detection method, a computer device, a storage medium, and a vehicle, to solve the problem of improving the accuracy of point cloud object detection. The method includes: obtaining a three-dimensional (3D) point cloud frame collected by a radar, performing object detection on the 3D point cloud frame to obtain a 3D object bounding box represented by 3D coordinates of bounding box corner points, and obtaining an object detection result based on the 3D object bounding box. Through the method, even if an object is covered, coordinates of uncovered end points of the object can be accurately obtained based on 3D coordinates of bounding box corner points in a 3D object bounding box, so that the accuracy of object detection can be effectively improved, and effective tracking corner points are provided for object tracking, thereby ensuring the accuracy and reliability of object tracking.

Abstract: An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.

Abstract: The invention discloses a preparation method for a vanadium-nitrogen alloy, which comprises the following steps: a, adding ammonium vanadate into a first rotary kiln for heating and deamination to obtain a thermal vanadium oxide and a mixed gas 1; b, adding the thermal vanadium oxide into a second rotary kiln, for heating and reducing in a first protective atmosphere to obtain a vanadium oxynitride and a mixed gas 2; c, mixing a graphite powder and the vanadium oxynitride in a ratio of K:1 by mass percentage to form a mixture, and mixing and molding the mixture to obtain a dried raw meal block, wherein the vanadium oxynitride has an oxygen content of 4%-20%, and the oxygen content is divided into n intervals, and the K value is in direct proportion to the oxygen content in each interval; and d, sending the dried raw material block into a calcining kiln for carbothermal reduction and nitridation in a second protective atmosphere to obtain a vanadium-nitrogen alloy and a mixed gas 3.

Abstract: To mitigate voltage droop while reducing the power and space consumed on the board and reducing switching activity, a clock skipping scheme may be implemented for an FPGA. The clock skipping scheme may be implemented in the FPGA design via an Electronic Design Automation (EDA) tool. The EDA tool may define clock skipping cycles based on customer needs for current ramp up speed (e.g., for an inrush current or an operating current) and clock frequency. The EDA tool may adjust clock skipping based on a power target and/or usage conditions of a user software design. In addition to mitigating voltage droop and reducing space consumed on the board and power consumed by the FPGA, the clock skipping scheme may maintain a base clock frequency, enable timing closure at the base clock frequency, and alleviate the need to reclose timing during clock skipping operations.

Abstract: An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.

Abstract: In a method for counting embryos developing in a uterus of Caenorhabditis elegans, a complete set of experimental procedures are designed to count embryos in the uterus of Caenorhabditis elegans by using Caenorhabditis elegans as a model organism. The method is applicable to Caenorhabditis elegans exposed from an L1 stage to a final stage of pregnancy, and can provide an easy-to-observe, fast, simple, accurate and reliable experimental method to apply Caenorhabditis elegans to research of reproductive ability, detection results of which are highly accurate and reliable, and the experimental method is suitable for promotion.

Abstract: An optical communication device includes a dispersion unit and a switching unit that are disposed in a cavity of a closed housing. The optical communication device further includes a monitoring unit and a drive unit. The monitoring unit may monitor in real time offsets of light spots formed on the switching unit. The drive unit can drive the switching unit based on a variation obtained by the monitoring unit, so that the switching unit compensates for the offsets of the light spots. In addition, the optical communication device may further include a dustproof and waterproof unit and a humidity control unit.

Abstract: An apparatus and method for redundant data processing with graceful degrading functionality. For example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements are to operate in a second redundancy mode excluding the one processing element.

Abstract: A torque module, a rotating shaft assembly, and an electronic device. The torque module includes a rotating shaft, a first blocking member, a second blocking member, a rotating assembly, a sliding assembly, and a first elastic member. The rotating assembly is sleeved on the rotating shaft and disposed between the first blocking member and the second blocking member, and the rotating assembly is arranged with a first mating portion. The sliding assembly includes a first sliding member sleeved on the rotating shaft, and the first sliding member is arranged with a second mating portion. The first elastic member is sleeved on the rotating shaft and disposed between the rotating assembly and the second blocking member. When the sliding assembly slides away from the rotating assembly, the first elastic member is compressed and the rotating assembly remains stationary relative to the sliding assembly when the rotating assembly stops rotating.

Abstract: One aspect of the present disclosure relates to an isolated mutant human estrogen receptor alpha (hER?) that may be used in methods of drug discovery. The isolated mutant hER? can include a DNA-binding domain (DBD), a ligand-binding domain (LBD), and an interface between the DBD and the LBD, wherein at least one tryptophan residue is mutated to a phenylalanine residue.

Abstract: A catalyst nanocomposite and methods of making the same. The catalyst nanocomposite includes a substrate; and a coating disposed on the substrate, the coating having a ruthenium and nitrogen co-doped carbon matrix. The coating may be melamine and formaldehyde and produced via pyrolizing the melamine and formaldehyde on a nanowire made of metals such as tellurium.

Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.

Abstract: Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.

Abstract: The present disclosure provides a method and an apparatus for user equipment (UE) registering, an electronic device and a storage medium. Under 5G core network slice isolation networking, when an AMF network element detects that a UE is unsuccessfully registered on the AMF network element, the AMF network element sends to the UE a registration reject message comprising at least a first cell and a second cell. In this way, when the UE sends registration information again, the UE can select target network slice information based on network slice information configured in the first cell. And a 5G base station, when receiving the registration information from the UE, determines a corresponding target AMF network element based on the target network slice information in the requested NSSAI, such that the UE can be successfully registered to the target AMF network element.