Patents by Inventor Yi-Ping Chao

Yi-Ping Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210084247
    Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin Yin, Po-Sheng Chou, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee
  • Publication number: 20200408885
    Abstract: A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
  • Publication number: 20200243510
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Publication number: 20200174105
    Abstract: Disclosed is a time-of-flight sensing apparatus and method.
    Type: Application
    Filed: October 17, 2019
    Publication date: June 4, 2020
    Inventors: Chin YIN, Meng-Hsiu WU, Chih-Lin LEE, Calvin Yi-Ping CHAO, Shang-Fu YEH
  • Patent number: 10636782
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 10638078
    Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao, Chih-Lin Lee, Chin Yin
  • Publication number: 20200119144
    Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: KUO-YU CHOU, SEIJI TAKAHASHI, SHANG-FU YEH, CHIH-LIN LEE, CHIN YIN, CALVIN YI-PING CHAO
  • Publication number: 20200018642
    Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 16, 2020
    Inventors: Chin Yin, Chih-Lin Lee, Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao
  • Patent number: 10510835
    Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
  • Publication number: 20190373200
    Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao, Chih-Lin Lee, Chin Yin
  • Publication number: 20190333989
    Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
    Type: Application
    Filed: April 27, 2018
    Publication date: October 31, 2019
    Inventors: KUO-YU CHOU, SEIJI TAKAHASHI, SHANG-FU YEH, CHIH-LIN LEE, CHIN YIN, CALVIN YI-PING CHAO
  • Patent number: 10277849
    Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Calvin Yi-Ping Chao, Chin-Hao Chang, Kuo-Yu Chou, Shang-Fu Yeh, Chih-Lin Lee, Chiao-Yi Huang
  • Publication number: 20190088640
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 10165208
    Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Calvin Yi-Ping Chao, Fu-Lung Hsueh, Honyih Tu, Jhy-Jyi Sze
  • Patent number: 10157906
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 10096645
    Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond pad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding strength between the sensor and the ASIC.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Ping-Yin Liu, Calvin Yi-Ping Chao, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Lan-Lin Chao
  • Publication number: 20180227531
    Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
    Type: Application
    Filed: March 30, 2018
    Publication date: August 9, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Calvin Yi-Ping Chao, Chin-Hao Chang, Kuo-Yu Chou, Shang-Fu Yeh, Chih-Lin Lee, Chiao-Yi Huang
  • Patent number: 9978796
    Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Min Liu, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh
  • Patent number: 9955096
    Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Calvin Yi-Ping Chao, Shang-Fu Yeh, Chin-Hao Chang, Chih-Lin Lee, Kuo-Yu Chou, Chiao-Yi Huang
  • Publication number: 20180040606
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee