Abstract: Involved is an isolated antigen binding protein, being capable of binding CCR8 derived from a primate animal. Further involved are a pharmaceutical composition comprising the antigen binding protein, and an application of the antigen binding protein and/or the pharmaceutical composition in the prevention and/or treatment of a tumor or a cancer.

Abstract: A set of primers and probes for simultaneous detection of Cymbidium mosaic virus (CymMV), Odontoglossum ringspot virus (ORSV), and Cymbidium ringspot virus (CymRSV) and a method for detecting CymMV, ORSV, and CymRSV, along with a method for their detection, are disclosed. The method involves designing multiplex real-time quantitative PCR detection primers and probes for CymMV, ORSV, and CymRSV and applying these primers and probes to the real-time quantitative PCR simultaneous detection of CymMV, ORSV, and CymRSV. It allows for faster detection of CymMV, ORSV, and CymRSV, taking only one-third of the time compared to uniplex real-time quantitative PCR technology, thereby reducing testing costs by approximately ? to ½ for each sample. The primers and probes are highly specific and sensitive, with a sensitivity as low as 1 to 10 copies. It provides an efficient and feasible detection method for early detection and prevention of CymMV, ORSV, and CymRSV.

Abstract: A method for preparing a microstructure on the surface of glass by titanium oxide nanoparticle-assisted infrared nanosecond laser, including the following steps: (1) dropwise applying a titanium oxide nanoparticle hydrogel onto the surface of a glass sample; (2) pressing another piece of glass on the surface of the hydrogel, so the hydrogel is evenly distributed between the two pieces of glass, and allowing the two pieces of glass to stand horizontally for a period of time to air-dry the hydrogel; (3) separating the two pieces of glass to obtain a glass with a uniform titanium oxide nanoparticle coating; (4) forming a microstructure using an infrared nanosecond laser with a wavelength of 1064 nm; and (5) performing after-treatment, including ultrasonically cleaning the sample with acetone, absolute ethanol and deionized water respectively for 10 min to remove titanium oxide nanoparticles attached to the surface, to obtain a glass sample with the microstructure.

Abstract: Provided are a bovine rotavirus fusion protein and calf diarrhea multivalent vaccine. The bovine rotavirus fusion protein contains a VP6 fragment, wherein the VP6 fragment contains an amino acid sequence as represented by SEQ ID NO. 4, and at least one loop region of the following (a)˜(c) is substituted with an antigenic epitope derived from bovine coronavirus and/or an antigenic epitope derived from E. coli: (a) amino acid residues of sites 168-177; with an amino acid sequence as represented by SEQ ID NO. 1; (b) amino acid residues of sites 194-205; with an amino acid sequence as represented by SEQ ID NO. 2; and (a) amino acid residues of sites 296-316, with an amino acid sequence as represented by SEQ ID NO. 3, The bovine rotavirus fusion protein contains a plurality of antigenic epitopes, and can enable a host to generate a plurality of antibodies after immunizing the host.

Abstract: A CaTiO3-based oxide thermoelectric material and a preparation method thereof are disclosed. The CaTiO3-based oxide thermoelectric material has a chemical formula of Ca1-xLaxTiO3, where 0<x?0.4. The present disclosure makes it possible to prepare a CaTiO3-based thermoelectric material with properties comparable to n-type ZnO, CaTiO3, SrTiO3 and other oxide thermoelectric materials. Among them, the La15 sample has a power factor reaching up to 8.2 ?Wcm?1K?2 (at about 1000 K), and a power factor reaching up to 9.2 ?Wcm?1K?2 at room temperature (about 300 K); and a conductivity reaching up to 2015 Scm?1 (at 300 K). The CaTiO3-based oxide thermoelectric material exhibits the best thermoelectric performance among calcium titanate ceramics. The method for preparing the CaTiO3-based oxide thermoelectric material of the present disclosure is simple in process, convenient in operation, low in cost, and makes it possible to prepare a CaTiO3-based ceramic sheet with high thermoelectric performance.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure.

Abstract: Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, an etch stop structure, and conductive contact structures. The stack structure includes conductive structures and insulative structures arranged in tiers. The stack structure includes sidewalls horizontally bounding the staircase structure. The staircase structure has steps includes edges of tiers of the stack structure. The first liner material is on the steps and the sidewalls and includes horizontally extending portions on the steps and vertically extending portions on the sidewalls. The etch stop structure is on the horizontally extending portions of the first liner material, the vertically extending portions of the first liner material being free of the etch stop structure. The conductive contact structures extend through the etch stop structure and the first liner material and to the conductive structures.

Abstract: A microelectronic device includes a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench includes a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions and at least one dielectric structure doped with one or more of carbon and boron on the dielectric liner material, the at least one dielectric structure horizontally overlapping the steps of the stadium structure.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: The present application relates to an all-optical detector and detection system, a response time test system, and a manufacturing method. The all-optical detector comprises a micro-nanofiber and an optical resonant cavity. The micro-nanofiber comprises transition regions and a uniform region. The uniform region is connected to the transition regions. The optical resonant cavity is provided in the uniform region. The optical resonant cavity is made of a semiconductor material. The all-optical detector provided in the present application detects light by means of the change of a resonance peak, achieves all-optical detection, and has a high signal-to-noise ratio.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A lining is formed in and that less-than-fills the cavity atop treads of the stairs. Individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. The lining that is atop the treads is replaced with at least one of metal material, polysilicon, or SiGe and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe. Conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe.

Abstract: Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions.

Abstract: Methods of forming a microelectronic device includes forming a preliminary stack structure including blocks separated by slots, each block including: tiers each including insulative material and sacrificial material; and live contact openings and support contact openings extending completely through the tiers. A first liner and a second liner are formed over surfaces of the preliminary stack structure. Portions of the second liner and the first liner within the support contact openings are removed without removing additional portions of the second liner and the first liner within the slots and the live contact openings. Fill material is formed within the slots, the live contact openings, and the support contact openings to form sacrificial slot structures, sacrificial contact structures, and support contact structures. The sacrificial contact structures are replaced with conductive contact structures.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conductive material of a lowest of the conductive tiers. Insulating material of the insulative tier that is immediately-directly above the lowest conductive tier is directly against a top of the conductive material of the lowest conductive tier. The insulating material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulative material. Other embodiments, including method, are disclosed.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.