Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer over the substrate, a first photodiode and a second photodiode in the first epitaxial layer, and a trench isolation structure between the first photodiode and the second photodiode. The first photodiode includes a first doped region having a first conductivity type. The first photodiode includes a second doped region, overlying the first doped region, having a second conductivity type different than the first conductivity type. The first photodiode includes a third doped region, overlying the first doped region, having the second conductivity type. A first distance between a sidewall of the third doped region and an uppermost surface of the first epitaxial layer is between about a hundredth to about a fifth of a second distance between a sidewall of the trench isolation structure and the uppermost surface of the first epitaxial layer.

Abstract: A light emitting apparatus has light emitting units. The light emitting units can be respectively provided with current densities, so that the light emitted by each of the light emitting unit has a light intensity, wherein the current densities are different from each other, or partial of the current densities are different from each other. A number of the light emitting units can be larger than or equal to four, all of the four lighting frequencies of the four light emitting units are different from each other, or partial of the four lighting frequencies of the four light emitting units are identical to each other, and the light emitting apparatus and the object under test rotate relative to each other. A light emitting method, a spectrum detection method and a lighting correction method are also illustrated for increasing SNR, correcting the light intensity or the spectrum signal.

Abstract: A fabricating method of a non-enzyme sensor element includes a printing step, a coating step and an electroplating step. In the printing step, a conductive material is printed on a surface of a substrate to form a working electrode, a reference electrode and an auxiliary electrode, and a porous carbon material is printed on the working electrode to form a porous carbon layer. In the coating step, a graphene film material is coated on the porous carbon layer of the working electrode to form a graphene layer. In the electroplating step, a metal is electroplated on the graphene layer by a pulse constant current to form a catalyst layer including a metal oxide.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.

Abstract: A switch device structure includes RF1-st and RF2-nd input terminals, RFA-th, RFB-th and RFC-th output terminals, P2A-th, P1B-th and P1C-th paths, and first and second common paths. The P2A-th path includes a first terminal, and a second terminal coupled to the RFA-th output terminal. The P1B-th path includes a first terminal, and a second terminal coupled to the RFB-th output terminal. The P1C-th path includes a first terminal, and a second terminal coupled to the RFC-th output terminal. The first common path is coupled to the RF2-nd input terminal and the first terminal of the P2A-th path. The second common path is coupled to the RF1-st input terminal, the first terminal of the P1B-th path, and the first terminal of the P1C-th path. The first and second common paths cross each other on different planes to form a crossover.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.

Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.

Abstract: A tray module is applicable to a chassis. The chassis includes at least two side plates. Each side plate has a guiding portion. The guiding portion includes a first horizontal section and an ascending section, and the ascending section is connected to the first horizontal section. The tray module includes a carrier body, at least two first connecting rods, and at least two second connecting rods. Each first connecting rod has a movable end and a driven end. The movable end is pivotally connected to the carrier body and slidably disposed in the guiding portions. Each second connecting rod has a pivotal end, a pivotal connection portion, and an operating end. The pivotal connection portion is located between the pivotal end and the operating end. Each pivotal end is pivotally connected to the each side plate. Each driven end is pivotally connected to each pivotal connection portion.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

Abstract: A tray module is applicable to a chassis. The chassis includes at least two side plates. Each side plate has a guiding portion. The guiding portion includes a first horizontal section and an ascending section, and the ascending section is connected to the first horizontal section. The tray module includes a carrier body, at least two first connecting rods, and at least two second connecting rods. Each first connecting rod has a movable end and a driven end. The movable end is pivotally connected to the carrier body and slidably disposed in the guiding portions. Each second connecting rod has a pivotal end, a pivotal connection portion, and an operating end. The pivotal connection portion is located between the pivotal end and the operating end. Each pivotal end is pivotally connected to the each side plate. Each driven end is pivotally connected to each pivotal connection portion.

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

Abstract: A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.