Patents by Inventor Yi Sheng Chen
Yi Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230049413Abstract: A tray module is applicable to a chassis. The chassis includes at least two side plates. Each side plate has a guiding portion. The guiding portion includes a first horizontal section and an ascending section, and the ascending section is connected to the first horizontal section. The tray module includes a carrier body, at least two first connecting rods, and at least two second connecting rods. Each first connecting rod has a movable end and a driven end. The movable end is pivotally connected to the carrier body and slidably disposed in the guiding portions. Each second connecting rod has a pivotal end, a pivotal connection portion, and an operating end. The pivotal connection portion is located between the pivotal end and the operating end. Each pivotal end is pivotally connected to the each side plate. Each driven end is pivotally connected to each pivotal connection portion.Type: ApplicationFiled: December 9, 2021Publication date: February 16, 2023Inventors: Si-Yun Tan, Yi-Sheng Chen
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Patent number: 11569363Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: GrantFiled: March 4, 2021Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Publication number: 20220359502Abstract: A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: YI-SHENG CHEN, KONG-BENG THEI, FU-JIER FAN, JUNG-HUI KAO, YI-HUAN CHEN, KAU-CHU LIN
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Publication number: 20220302108Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
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Patent number: 11417649Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.Type: GrantFiled: November 30, 2018Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Sheng Chen, Kong-Beng Thei, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin
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Patent number: 11302691Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.Type: GrantFiled: September 2, 2020Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
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Publication number: 20210343707Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.Type: ApplicationFiled: July 8, 2021Publication date: November 4, 2021Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
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Publication number: 20210280577Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: ApplicationFiled: May 10, 2021Publication date: September 9, 2021Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
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Patent number: 11063038Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.Type: GrantFiled: March 25, 2020Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
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Publication number: 20210193813Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: ApplicationFiled: March 4, 2021Publication date: June 24, 2021Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Patent number: 11004844Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: GrantFiled: July 25, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
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Patent number: 10964692Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.Type: GrantFiled: September 21, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
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Patent number: 10950708Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: GrantFiled: November 14, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Patent number: 10937785Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.Type: GrantFiled: March 4, 2016Date of Patent: March 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Sheng Chen, Kong-Beng Thei, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin
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Patent number: 10916542Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: GrantFiled: March 4, 2016Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
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Publication number: 20200402978Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
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Patent number: 10790279Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.Type: GrantFiled: October 18, 2019Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
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Publication number: 20200243516Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.Type: ApplicationFiled: March 25, 2020Publication date: July 30, 2020Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
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Publication number: 20200235658Abstract: An operation method for a DC/DC converter includes: using a power stage for converting a DC input voltage into a DC output voltage, the power stage including an inductor; detecting whether the DC output voltage has an overshoot when the DC/DC converter is switched from a heavy loading into a light loading; when it is determined that the DC output voltage has the overshoot, forcing the DC/DC converter for additionally maintaining at a force continuous conduction mode (CCM) and thus discharging the DC output voltage by the inductor, and controlling the DC/DC converter switching from the force CCM into a discontinuous conductor mode (DCM).Type: ApplicationFiled: April 26, 2019Publication date: July 23, 2020Inventors: Yi-Sheng CHEN, Yu-Shen LIN, Wei-Hsin WEI
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Patent number: 10629592Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure is in the first and second IC dies and extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure. The plurality of TSV coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.Type: GrantFiled: May 25, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen