Patents by Inventor Yi-Shin Tung

Yi-Shin Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10635484
    Abstract: A multi-core processing device includes a first processor core and a second processor core. The computation capability of the second processor core is greater than that of the first processor core. When loading of a task is lower than an hmp_down_migration threshold, the multi-core processing device allocates the task to the first processor core. When the loading of a task is higher than an hmp_up_migration threshold, the multi-core processing device allocates the task to the second processor core. At least one of the hmp_down_threshold and the hmp_up_threshold changes from a first value to a second value during a run time of the multi-core processing device.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 28, 2020
    Assignee: MEDIATEK INC.
    Inventors: Yi-Shin Tung, Tse-Tsung Shih, Tzu-Jung Huang
  • Publication number: 20190289300
    Abstract: A method for compressing an image frame. Display data of a plurality of image blocks in the image frame is transmitted in a raster san order to a post-processing circuit. Upon receiving the display data of one image block, the post-processing circuit reads intermediate data of a buffering image block corresponding to the image block from a buffer memory, performs post-processing on the intermediate data of the buffering image block and display data of a main sub-block in the image block according to the display data of the image block and the intermediate data of the buffering image block to generate post-processed data of a post-processed image block, and stores the intermediate data of an intermediate image block in the image block to the buffer memory. A compressor compresses the post-processed data of the post-processed image block into compression data of the post-processed image block.
    Type: Application
    Filed: September 25, 2018
    Publication date: September 19, 2019
    Inventors: Yi-Chin HUANG, Yi-Shin TUNG
  • Patent number: 10264267
    Abstract: A method for compressing image data is provided. The image data includes a file to be compressed, which includes N blocks to be compressed. The method includes: setting a target data increment of each of the N blocks of the file according to a 0th accumulated target data size and an Nth accumulated target data size; before compressing an nth block, calculating an (n?1)th accumulated target data size of an (n?1)th block according to the 0th accumulated target data size and the target data increment; when a difference between an (n?1)th accumulated compressed data size and the (n?1)th accumulated target data size is smaller than a predetermined threshold, removing X least significant bit(s) of a plurality of sets of data in the nth block to generate an updated nth block; and compressing the updated nth block to generate a compressed nth block.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 16, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yi-Chin Huang, Yi-Shin Tung
  • Patent number: 10116952
    Abstract: A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: October 30, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: He-Yuan Lin, Ya-Ting Yang, Yi-Shin Tung
  • Patent number: 10026149
    Abstract: An image processing system includes an image processing module, a frame buffer encoding module and a frame buffer. Each image block includes multiple first-type coding blocks and at least one second-type coding block. The image processing module generates a first image processed result according to multiple first-type coding blocks of a target image block. The frame buffer encoding module generates a first frame buffer encoded result according to the first image processed result. The frame buffer, for the target image block, provides a buffer region including at least one first random access point and a second buffer region including at least one second random access point. The first frame buffer encoded result is stored to the first buffer region. At least one second-type coding block of the target image block is stored to the second buffer region.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 17, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yi-Shin Tung, Chia-Chiang Ho
  • Publication number: 20180199002
    Abstract: A video processing apparatus includes a down-sampling circuit, a combining circuit, a metadata generating circuit, and an encoder. The down-sampling circuit down-samples P videos according to predetermined picture layout information of K picture layouts. Each of the videos corresponds to a television program. The combining circuit combines the P down-sampled videos according to the predetermined picture layout information to generate combined videos corresponding to the K picture layouts. The metadata generating circuit generates metadata that describes television program information corresponding to the picture layouts according to the predetermined picture layout information. The encoder encodes the combined videos and the metadata to image data that conforms to a predetermined broadcast format for a television broadcasting system to broadcast.
    Type: Application
    Filed: September 25, 2017
    Publication date: July 12, 2018
    Inventors: Yi-Shin Tung, Tzu-Jung Huang, He-Yuan Lin
  • Patent number: 10015493
    Abstract: An encoding apparatus includes an intra-prediction module, a transform module and a control module. The intra-prediction module performs intra-prediction on an image block in a video frame according to a plurality of sets of reference image data to generate a residual block. The reference image data includes a set of reference image data corresponding to a predetermined side of the image block. The transform module performs preliminary transform on the residual block to generate a preliminary transform coefficient matrix. According to whether at least one of the reference image data corresponding to the predetermined side is generated according to image data of an adjacent pixel of the image block, the control module determines whether secondary transform perpendicular to the predetermined side is to be performed on a low-frequency component sub-matrix in the preliminary transform coefficient matrix.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 3, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: He-Yuan Lin, Yi-Shin Tung
  • Publication number: 20180157527
    Abstract: A multi-core processing device includes a first processor core and a second processor core. The computation capability of the second processor core is greater than that of the first processor core. When loading of a task is lower than an hmp_down_migration threshold, the multi-core processing device allocates the task to the first processor core. When the loading of a task is higher than an hmp_up_migration threshold, the multi-core processing device allocates the task to the second processor core. At least one of the hmp_down_threshold and the hmp_up_threshold changes from a first value to a second value during a run time of the multi-core processing device.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 7, 2018
    Inventors: Yi-Shin Tung, Tse-Tsung Shih, Tzu-Jung Huang
  • Publication number: 20180115779
    Abstract: An image processing apparatus for reconstructing an image frame including multiple image segments is provided. The multiple image segments are converted to a bitstream through entropy encoding. The image processing apparatus includes a shared storage region, a first processor and a second processor. The first processor performs entropy decoding on the bitstream to generate a set of first symbols, reconstructs a first image segment according to the set of first symbols, and stores the reconstructed first image segment into the shared storage region. The second processor also performs entropy decoding on the bitstream to generate a set of second symbols, obtains the part of the reconstructed image segment that is associated with a second image segment, and reconstructs the second image segment according to the set of second symbols and the obtained part of the first image segment.
    Type: Application
    Filed: February 6, 2017
    Publication date: April 26, 2018
    Inventors: Sung-Wen Wang, Yi-Shin Tung
  • Publication number: 20180054626
    Abstract: A method for decoding audio/video data in an Audio Video coding Standard (AVS) system is provided. A predetermined upper limit of an offset shift, greater than zero and smaller than an upper limit of a range shift, is provided. Whether to terminate an offset pre-fetching process is determined according to whether an offset shift reaches the upper limit of the offset shift. After offset shift pre-fetching process is terminated, a most significant bit (MSB) of a valid offset is preserved. The preserved valid MSB of the valid offset is used as a reference when a symbol to be decoded is determined to be a most probable symbol or a least probable symbol.
    Type: Application
    Filed: March 15, 2017
    Publication date: February 22, 2018
    Inventors: He-Yuan Lin, Yi-Shin Tung
  • Publication number: 20170353728
    Abstract: A method for compressing image data is provided. The image data includes a file to be compressed, which includes N blocks to be compressed. The method includes: setting a target data increment of each of the N blocks of the file according to a 0th accumulated target data size and an Nth accumulated target data size; before compressing an nth block, calculating an (n?1)th accumulated target data size of an (n?1)th block according to the 0th accumulated target data size and the target data increment; when a difference between an (n?1)th accumulated compressed data size and the (n?1)th accumulated target data size is smaller than a predetermined threshold, removing X least significant bit(s) of a plurality of sets of data in the nth block to generate an updated nth block; and compressing the updated nth block to generate a compressed nth block.
    Type: Application
    Filed: April 12, 2017
    Publication date: December 7, 2017
    Inventors: Yi-Chin Huang, Yi-Shin Tung
  • Publication number: 20170324967
    Abstract: A method for controlling bitstream decoding is provided. The bitstream includes a plurality of frames. The method includes: generating a performance indicator according to a decoding time of at least one previous frame; generating a dropping decision according to the performance indicator, wherein the dropping decision indicates whether it is needed to drop a frame; and determining whether to drop a current frame according to the dropping decision.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 9, 2017
    Inventors: Ya-Ting Yang, Yi-Shin Tung
  • Publication number: 20170264910
    Abstract: A video stream decoding system includes a video decoder, a frame encoder and a buffer. The frame encoder includes a prediction unit and a compressor. The prediction unit predicts an image data group in a prediction block of a frame to generate a predicted image data group. The prediction image data group includes a first sub predicted image data group and a second sub predicted image data group. The compressor compresses the first sub predicted image data group in a unit of the first sub predicted image data group to generate a first compressed image data group, and compresses the second sub predicted image data group in a unit of the second sub predicted image data group to generate a second compressed data image group.
    Type: Application
    Filed: October 17, 2016
    Publication date: September 14, 2017
    Inventors: Yi-Chin Huang, Yi-Shin Tung
  • Publication number: 20170201707
    Abstract: A television managing apparatus cooperating with a remote controller includes a receiver and a controller. The receiver receives an instruction sent from the remote controller. The controller actives a performance optimization process in response to each latest instruction that the receiver receives.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 13, 2017
    Inventors: Yi-Shin Tung, He-Yuan Lin, Hung-Wei Yang
  • Publication number: 20170201765
    Abstract: A video stream decoding system includes a video decoder, a frame encoder, a buffer and a frame decoder. The video decoder receives a video stream, and decodes an encoded frame in the video stream to generate a frame. The frame includes a plurality of coding blocks. The frame encoder includes a first compressor, a second compressor and a selector. The first compressor compresses an image data group in a coding block according to a first compression algorithm to generate a first compressed image data group. The second compressor compresses the image data group in the coding block according to a second compression algorithm to generate a second compressed image data group. The first compression algorithm is different from the second compression algorithm.
    Type: Application
    Filed: February 4, 2016
    Publication date: July 13, 2017
    Inventors: Yi-Chin HUANG, Yi-Shin TUNG
  • Publication number: 20170155918
    Abstract: A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.
    Type: Application
    Filed: January 11, 2016
    Publication date: June 1, 2017
    Inventors: He-Yuan LIN, Ya-Ting YANG, Yi-Shin TUNG
  • Patent number: 9615133
    Abstract: A control module of a multimedia device for generating display data required by a display module is provided. The control module includes: a signal receiving and analyzing unit, configured to receive a first signal to accordingly generate a pre-boot command, and to receive a second signal to accordingly generate a boot command; and a processor, configured to perform a pre-boot process according to the pre-boot signal to generate the image data, to enter a waiting mode when the pre-boot process is complete, and to exit the waiting mode according to the boot command. The image data is not used to display an image by the display module when the processor remains in the waiting mode.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 4, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ling-Hsuan Huang, Sung-Wen Wang, Yi-Shin Tung
  • Publication number: 20170060640
    Abstract: A routine task allocating method of a multicore computer is provided. The multicore computer includes processor that includes a plurality of processing cores. The allocating method includes following steps. According to the number of the processing cores, a routine task is divided into a plurality of routine sub-tasks. The number of the routine sub-tasks is greater than or equal to the number of the processing cores. The routine sub-tasks are allocated according to an operation status of the multicore computer. Allocating the routine sub-tasks includes setting an execution sequence the routine sub-tasks as well as binding relationships between the routine sub-tasks and the processing cores.
    Type: Application
    Filed: October 27, 2015
    Publication date: March 2, 2017
    Inventors: Chih-Sheng Wang, Yi-Shin Tung
  • Publication number: 20170061573
    Abstract: An image processing system includes an image processing module, a frame buffer encoding module and a frame buffer. Each image block includes multiple first-type coding blocks and at least one second-type coding block. The image processing module generates a first image processed result according to multiple first-type coding blocks of a target image block. The frame buffer encoding module generates a first frame buffer encoded result according to the first image processed result. The frame buffer, for the target image block, provides a buffer region including at least one first random access point and a second buffer region including at least one second random access point. The first frame buffer encoded result is stored to the first buffer region. At least one second-type coding block of the target image block is stored to the second buffer region.
    Type: Application
    Filed: July 13, 2016
    Publication date: March 2, 2017
    Inventors: Yi-Shin Tung, Chia-Chiang Ho
  • Patent number: 9563345
    Abstract: A method for controlling an electronic device is provided. The method includes detecting a first tilt angle between the electronic device and a reference plane, and controlling the electronic device to perform an operating according to the first tilt angle. The operation is associated with a user interface operation or an audio/video playback operation.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 7, 2017
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yi-Shin Tung, Yi-Chin Huang, Chia-Chiang Ho