Abstract: A video codec method synchronizes long term reference frames in a video encoding device and a video decoding device of a video communication system. The video encoding device encodes video frames to code streams in an inter-prediction mode and set the corresponding reference frames to non-committed long term reference frames. The video decoding device decodes the code streams using the corresponding reference frames, then transmits an acknowledgement of the non-committed long term reference frames to the video encoding device. The video encoding device sets the non-committed long term reference frames to committed long term reference frames, and encodes succeeding video frames in the inter-prediction mode using the committed long term reference frames.

Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises first and second arithmetic logic units (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive the result from the path in a clock cycle subsequent to the first clock cycle.

Abstract: A decoder for decoding a message using an arbitrary-side growing (ASG) Huffman tree including a plurality of codewords and symbols includes a database, a processing module, and a bit pattern matching module. The database stores a plurality of parameters corresponding to the ASG Huffman tree divided into several sub-trees according to a Hashemian cut operation and a bits-pattern-Xor (BPX) operation. The plurality of parameters include a bit pattern of a sub-tree of the ASG Huffman tree divided according to the BPX operation and a code length of the bit pattern. The processing module receives a bit stream corresponding to the ASG Huffman tree from an encoder. The bit pattern matching module selects bits from the bit stream according to the code length of the bit pattern and decodes the selected bits into a symbol in the ASG Huffman tree by comparing the selected bits with the bit pattern.

Abstract: A decoder for decoding a message using an arbitrary-side growing (ASG) Huffman tree including a plurality of codewords and symbols includes a database, a processing module, and a bit pattern matching module. The database stores a plurality of parameters corresponding to the ASG Huffman tree divided into several sub-trees according to a Hashemian cut operation and a bits-pattern-Xor (BPX) operation. The plurality of parameters include a bit pattern of a sub-tree of the ASG Huffman tree divided according to the BPX operation and a code length of the bit pattern. The processing module receives a bit stream corresponding to the ASG Huffman tree from an encoder. The bit pattern matching module selects bits from the bit stream according to the code length of the bit pattern and decodes the selected bits into a symbol in the ASG Huffman tree by comparing the selected bits with the bit pattern.