Abstract: A system for testing hardware devices applies a multi-level architecture including a Graphical User Interface (GUI) level (10), a Dynamic Link Library (DLL) level (20), and a device driving level (30). The GUI level selects test items and test units for a test project based on test requirements, stores the test project in a test script file, configures test parameters for performing the test project, and stores the test parameters in a test parameter configuration file. The DLL level transmits test results of each hardware device (108) to the GUI level. The device driving level includes a device driving module (107) for obtaining test information on the hardware device, comparing the test information with standard information in the test parameter configuration file, and generating a comparison result. A related method is also disclosed.

Abstract: The invention provides a digital television tuner having at least two brances that receive a radio frequency signal, wherein the radio frequency signal carries M channels (M is a positive integer). A target image data is generated in real time since at least one of the branches pre-extracts the image compression data of the next channel to be switched to.

Abstract: A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times to generate a first sampled signal. The data delay buffer decides a sampling range of the first sampled signal and outputs a second sampled signal. The sampling range selector picks a part of bits of the second sampled signal and outputs output data. The weighted detecting module outputs a phase shifting signal responding to the output data. The first loop filter outputs a first adjusting signal. The first sampling window module outputs a phase selecting signal. The second loop filter outputs the recovery signal and a second adjusting signal. The second sampling window module outputs the first phase checking signal and the second phase checking signal. The phase picking module outputs the output data.

Abstract: A sputtering target having at least one flat first sputtering surface and at least one second sputtering surfaces respectively and laterally abutted against the flat first sputtering surface and slanting in one direction relative to the first sputtering surface. By means of adjusting the position of the second sputtering surface related to the first sputtering surface and utilizing the differently slanted second sputtering surface of the sputtering target, the distribution of the thin film deposited on the surfaced of a substrate is relatively controlled and a uniform thickness of the thin film is obtained.

Abstract: A memory access apparatus is disclosed. The apparatus comprising: a memory access module, having a first interface and a second interface; a first bus, coupled to the first interface; a first memory, coupled to the first bus, for storing a first data; a second bus, coupled to the second interface; and a second memory, coupled to the second bus, for storing a second data; wherein said memory access module accesses said first memory or said second memory or both according to the using statuses of said first bus and said second bus.

Abstract: The present invention discloses a circuit capable of self-correcting delay time that includes a clock generating unit for generating a clock signal, a processing unit for producing a counter enable signal according to a reference clock, and a counting unit for receiving the counter enable signal and using the clock signal to count the reference clock for producing a count value, and the count value is returned to the processing unit for performing an analysis to obtain a delay time. The present invention can effectively overcome the shortcomings of the prior art that requires a delay circuit to make corrections one by one, and thus the invention can greatly save the time, manpower, and cost incurred.

Abstract: The present invention provides a method and apparatus for performing read phase auto-calibration of a storage device. The method includes writing the data with at least one predetermined pattern into the storage device, reading the data according to a read phase of a plurality of read phases, comparing the predetermined pattern with the data, and selecting a read phase from the plurality of read phases according to the comparing result.

Abstract: A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.

Abstract: A system for programming at least a controller chip is disclosed. The system includes a programming apparatus and at least a programmable device mounted on the programming apparatus. The programming apparatus has at least a first connection interface and a micro-controller. The programmable device has the monitor controller chip mounted thereon and a second connection interface coupled between the first connection interface and the controller chip. The micro-controller controls the programming of the controller chip.

Abstract: A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.

Abstract: An exemplary system for testing a serial port includes a serial port (106), a female cable connector (108) connected to the serial port, and an optical-coupled chip (110) connected to the female cable connector. The serial port, the female cable connector and the optical-coupled chip collectively form a circular loop. The system further includes a transmitting module (124), a receiving module (126) and a determining module (128). The transmitting module is configured for transmitting data into the circular loop. The receiving module is configured for receiving data from the circular loop. The determining module is configured for comparing the transmitted data and the received data, and determining whether the serial port is in predetermined working condition according to the comparison result. A related method is also provided.

Abstract: A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.

Abstract: An Audio Codec which comprises a power selecting circuit an audio compiler circuit and a control amplifier circuit. The power selecting circuit receives at least a primary power source and an auxiliary power source and outputs a working power selected from the power sources. The auxiliary power source is selected and output to the control amplifier circuit only when the computer is at a power-off status. When the computer is power-on, the primary power source will be selected and output to both the audio compiler circuit and the control amplifier circuit. Therefore, the Audio Codec of the present invention only needs one set of internally furnished control amplifier circuit to both operate on the normal power-on status and perform the Power OFF CD function.

Abstract: An audio converting device including a digital high-pass filter, an expander, a digital low-pass filter, a delta-sigma modulator, a digital-to-analog converter, an analog low-pass filter and a gain control unit is provided. The digital high-pass filter in this invention can filter out a direct-current component of digital audio data such that the production of noise is avoided when the volume is adjusted by users.

Abstract: The invention is related to a method and an apparatus for generating an output clock. The method comprises: measuring a reference clock according to a free-run clock to produce a counter signal in a normal mode; suspending the reference clock; and generating the output clock according to the counter signal and the free-run clock in a power-saving mode.

Abstract: A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting unit. The reset unit outputs reset signals according to the first and second input signals so as to reset the phase error detecting unit without delay time. Thus, it is possible to make the output timing of the phase error signal in a more precisely linear proportion to the phase error value and to enhance the sensitivity of the phase locked loop.

Abstract: A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.

Abstract: A multi-jack detector for detecting states of a plurality of jacks. Each jack comprises a first switch having a first normally closed terminal and a first output terminal. The multi-jack detector comprises a plurality of bias resistors each coupled to one of the first output terminals, respectively; a control unit for determining the states of the plurality of jacks; wherein the first normally closed terminals are commonly coupled to a first node and the control unit determines the states of the plurality of jacks according to a voltage at the first node. Because the voltage at the first node is different for each state of the jacks, the detector can detects the states of the jacks using a single I/O pin.

Abstract: A system for testing hardware devices applies a multi-level architecture including a Graphical User Interface (GUI) level (10), a Dynamic Link Library (DLL) level (20), and a device driving level (30). The GUI level selects test items and test units for a test project based on test requirements, stores the test project in a test script file, configures test parameters for performing the test project, and stores the test parameters in a test parameter configuration file. The DLL level transmits test results of each hardware device (108) to the GUI level. The device driving level includes a device driving module (107) for obtaining test information on the hardware device, comparing the test information with standard information in the test parameter configuration file, and generating a comparison result. A related method is also disclosed.

Abstract: A method for capturing computer system configuration information of a computer includes the steps of: initializing a Component Object Model (COM) application programming interface of the computer; accessing a WMI (Windows Management Instrumentation) name space of the computer; creating objects for classes in the WMI name space; and capturing computer system configuration information on the computer from the objects. Another method for checking computer system configuration information on a client computer through a server computer includes the steps of: connecting the server computer with the client computer; capturing the client computers' computer system configuration information through each client computer's WMI; comparing the captured computer system configuration information with the predetermined computer system configuration information; and reporting the comparing result. A system for checking computer system configuration information is also disclosed.