Abstract: A method includes obtaining a current picture block, using a 4:4:4 sampling format for the current picture block. The current picture block includes three 2W×2H sample arrays, one 2W×2H sample array represents a first chrominance component, one 2W×2H sample array represents a second chrominance component, and one 2W×2H sample array represents a luminance component. The method further includes separately downsampling the first chrominance component and the second chrominance component of the current picture block to obtain a base layer picture block, where a 4:2:0 sampling format is used for the base layer picture block, obtaining a differential chrominance picture block based on the current picture block, where the differential chrominance picture block includes at least part of chrominance samples of the current picture block, encoding the base layer picture block to obtain a base layer bitstream, and encoding the differential chrominance picture block to obtain an enhancement layer bitstream.

Abstract: This application provides a picture encoding and decoding method and apparatus. The picture encoding method provided includes: obtaining a to-be-processed picture block, where a dimension of the picture block is 2×2, and a chroma sampling rate of the picture block is higher than that of YUV4:2:0; obtaining a base layer picture block and an enhancement layer picture block based on the picture block, where a chroma sampling rate of the base layer picture block is lower than the chroma sampling rate of the picture block, and a pixel included in a first chroma component of the enhancement layer picture block does not overlap a pixel included in a first chroma component of the base layer picture block; performing encoding based on the base layer picture block to obtain a base layer bitstream; and performing encoding based on the enhancement layer picture block to obtain an enhancement layer bitstream.

Abstract: A method of programming non-volatile memory cells comprising determining a target read current for respective ones of the memory cells based upon incoming data, associating respective ones of the memory cells with a respective one of a plurality of cell groups based upon the determined target read current for the respective memory cell being within a target read current range associated with the respective cell group, fast programming respective ones of the memory cells to a coarse target read current associated with the cell group to which the respective memory cell is associated, wherein the coarse target read current for respective ones of the cell groups is greater than the target read current range for the respective cell group, and then slow programming respective ones of the memory cells until the target read current determined for the respective memory cell is achieved.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface with a semiconductor member extending vertically from the upper surface, wherein the semiconductor member has a first conductivity type. A first region of a second conductivity type different than the first conductivity type is formed at a proximal end of the semiconductor member adjacent the upper surface. A second region of the second conductivity type is formed at a distal end of the semiconductor member. A channel region of the semiconductor member extends between the first and second regions. A floating gate laterally wraps around a first portion of the channel region. A control gate laterally wraps around the floating gate. A select gate laterally wraps around a second portion of the channel region. An erase gate laterally wraps around the semiconductor member.

Abstract: A welded component for a substrate processing system includes a first component comprised of a first semiconductor material, a second component comprised of the first semiconductor material, a weld region defined between respective unwelded regions of the first component and the second component located on either side of the weld region, and a seam defined in the weld region between the first component and the second component. The weld region is comprised of the first semiconductor material of respective portions of the first component and the second component on either side of the seam that was melted and recrystallized to form the weld region.

Abstract: A nanosheet device is provided that has high quality epitaxially grown source/drain regions and reduced parasitic capacitance which are afforded by forming an air gap between an epitaxially grown source/drain region and a semiconductor substrate. The isolation provided by the air gap does not need to extend beneath the channel region of the nanosheet device.

Abstract: A method of programming memory cells that includes reading the memory cells to determine respective read currents for the memory cells. Respective ones of the memory cells are assigned to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read currents, such that the determined read current for a respective one of the memory cells is within the range of read currents for the group of the memory cells to which the memory cell is assigned. The memory cells are programmed using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.

Abstract: Described herein is a system with a first network element and a second network element. The first network element contains a processor configured to synchronize with the second network element; and maintain synchronization with the second network element. The first network element is a small cell eNB and the second network element is one of the following: a macro cell enhanced node-B (eNB); or a small cell eNB.

Abstract: An adjustment mechanism for an adjustment device comprising a main worm gear wheel having a hollow central passage and a main worm. The main worm gear wheel is held in an injection molded plastic housing having at least one opening axially aligned with the central passage to allow a shaft to extend via the opening into the central axial passage to be in supporting engagement with the main gear. The main worm is held in the housing for rotation about a main axis of the main worm, and includes at least one circumferential spiral tooth in intermeshing arrangement with teeth on the circumference of the main worm gear wheel, and can be driven to rotation relative to the housing about its main worm axis. Stiffeners are provided between the housing and the main worm gear wheel and/or the main worm to lock the intermeshing arrangement of the teeth under torque.

Abstract: Disclosed are an encoding/decoding method, apparatus, and system. In an implementation, the encoding method includes: encoding video information, where the video information includes M frames, the M frames include a first frame, a second frame, and a third frame, the second frame refers to the first frame, and the third frame refers to the second frame or the first frame, storing the first frame, the second frame, and the third frame in a buffer to obtain candidates of a long-term reference frame, and selecting a subset from the candidates based on a feedback signal as a long-term reference frame.

Abstract: A dongle device and a firmware updating method are provided. The dongle device includes a connector, a communication module, a storage module, and a control module. The storage module is configured to store a device ID and a first image file. The control module is electrically connected to the connector, the communication module, and the storage module. The control module is configured to output an updating command to an electronic device through the connector, control the communication module to scan and to wirelessly receive a broadcast packet broadcasted by the electronic device, control the communication module to establish a wireless connection between the dongle device and the electronic device according to the broadcast packet, and use the first image file to update a firmware of the electronic device via the wireless connection. The updating command and the broadcast packet have the same device ID.

Abstract: An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by receiving a desired amount of variation from a baseline erase pulse parameter, generating a first erase pulse that includes the desired amount of variation from the baseline erase pulse parameter, and applying the first erase pulse to the block of memory cells. The desired amount of variation from the baseline erase pulse is selected to reduce erase-induced damage to the block of memory cells.

Abstract: Described herein is a system with a first network element and a second network element. The first network element contains a processor configured to synchronize with the second network element; and maintain synchronization with the second network element. The first network element is a small cell eNB and the second network element is one of the following: a macro cell enhanced node-B (eNB); or a small cell eNB.

Abstract: Provided is an intelligent design method of a type I diabetes vaccine. The method according to the disclosure includes following steps: performing a computer-simulated amino acid mutation design on initial type I diabetes autoantigen sequences obtained from patients with type I diabetes, accompanied with a rational design based on a structure of an HLA-polypeptide molecule-TCR ternary complex.

Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.

Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

Abstract: Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.

Abstract: A prediction method for formation water yield of carbonate gas reservoir is provided, which includes: S1, constructing an initial prediction model for a formation water yield of a carbonate gas reservoir; S2, collecting and pre-processing raw data; where the raw data is raw data of parameters of the initial prediction model, and the raw data further includes raw data of a permeability when the initial prediction model does not involve permeability; S3, performing, according to the pre-processed raw data, an uncertainty analysis and a dimension reduction process on the parameters of the initial prediction model; S4, constructing a target prediction model for the formation water yield of the carbonate gas reservoir according to a result of dimension reduction process; and S5, obtaining, according to the target prediction model for formation water yield of carbonate reservoir, a predictive probability solution of formation water yield by combining a result of uncertainty analysis.

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.