Abstract: A display substrate and a display apparatus are provided. The display substrate includes sub-pixels, a pixel defining pattern, and a defining structure. The sub-pixel includes a light-emitting functional layer. The pixel defining pattern includes first openings and second openings, a portion in the defining structure exposed by the second opening is configured to isolate the light-emitting functional layer. The sub-pixels include a first sub-pixel and a second sub-pixel, a turn-on voltage of the first sub-pixel is higher than that of the second sub-pixel; the defining structure includes a first defining structure surrounding the second sub-pixel and a second defining structure surrounding the second sub-pixel; the first defining structure is not exposed by the second opening; or a proportion of the first defining structure exposed by the second opening is less than a proportion of the second defining structure exposed by the second opening.

Abstract: The present disclosure relates to the fields of radiopharmaceuticals and nuclear medicine and provides a precursor composition of HER2 affibody, comprising: HEPES, sodium glucoheptonate, stannons chloride and an HER2 affibody, wherein the composition is free of vitamin C and cysteine, and the composition is a lyophilized powder.

Abstract: Provided is an intelligent design method of a type I diabetes vaccine. The method according to the disclosure includes following steps: performing a computer-simulated amino acid mutation design on initial type I diabetes autoantigen sequences obtained from patients with type I diabetes, accompanied with a rational design based on a structure of an HLA-polypeptide molecule-TCR ternary complex.

Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.

Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

Abstract: Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.

Abstract: A prediction method for formation water yield of carbonate gas reservoir is provided, which includes: S1, constructing an initial prediction model for a formation water yield of a carbonate gas reservoir; S2, collecting and pre-processing raw data; where the raw data is raw data of parameters of the initial prediction model, and the raw data further includes raw data of a permeability when the initial prediction model does not involve permeability; S3, performing, according to the pre-processed raw data, an uncertainty analysis and a dimension reduction process on the parameters of the initial prediction model; S4, constructing a target prediction model for the formation water yield of the carbonate gas reservoir according to a result of dimension reduction process; and S5, obtaining, according to the target prediction model for formation water yield of carbonate reservoir, a predictive probability solution of formation water yield by combining a result of uncertainty analysis.

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.

Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

Abstract: To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some embodiments, the programming comprises applying doses of a programming signal and the gate to channel voltage differential is only created for a subset of the time periods between doses of the programming signal.

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.

Abstract: An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.

Abstract: A method for performing a programming operation with respect to a memory structure. The method comprises: (1) initiating a programming operation with respect to multiple program states of a non-volatile memory structure; (2) programming each of the multiple program states according to a programming order; and (3) after completing the programming of each of the multiple program states, programming an erase state as the final program state of the programming order.

Abstract: This application provides a spherical image processing method which includes: obtaining a spherical image and determining a sphere center of the spherical image; determining a viewpoint of a user when the user views the spherical image, where the viewpoint is located at any point, other than the sphere center, in a sphere space surrounded by the spherical image; determining a pixel expansion region and a pixel shrinkage region on the spherical image based on the sphere center and the viewpoint; and performing an image processing operation on the spherical image, where the image processing operation comprises a pixel expansion processing operation on an image in the pixel expansion region, and a pixel shrinkage processing operation on an image in the pixel shrinkage region.

Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.

Abstract: This application provides a picture encoding method and apparatus, and a picture decoding method and apparatus. The picture encoding method in this application includes: determining a reference frame number of a current picture based on channel feedback information, where the channel feedback information indicates information about a picture frame received by a decoder side; obtaining a first reference layer number set of a first picture frame corresponding to the reference frame number, where the first reference layer number set includes layer numbers of N1 layers, 1?N1<L1, and L1 indicates a total quantity of layers of the first picture frame; determining a reference layer number of the current picture based on the channel feedback information and the first reference layer number set; and performing video encoding on the current picture based on the reference frame number and the reference layer number to obtain a bitstream.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.