Patents by Inventor Yi Song

Yi Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770361
    Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Veeraraghavan S. Baskar, Jay W. Strane, Ekmini Anuja De Silva
  • Publication number: 20200273857
    Abstract: A semiconductor structure includes a decoupling capacitor on a semiconductor substrate. The decoupling capacitor includes a multilayer stack structure having one or more active regions on a top surface thereof. The semiconductor structure further includes one or more semiconductor devices on the one or more active regions on the decoupling capacitor.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Inventors: Juntao Li, Kangguo Cheng, Yi Song
  • Publication number: 20200266871
    Abstract: The present invention is a method and system for supporting a beamforming antenna system in a mobile broadband communication network with an improved beam pattern, beam sweep pattern, pilot channel design with feedback and reporting rules, and control signaling design. Specifically, the improved beam pattern includes a method of supporting wireless communications in a wireless network forming at least two spatial beams within a cell segment where the at least two spatial beams are associated with different power levels, and separately, where at least two spatial beams can be moved across the cell segment according to a unique sweep pattern. The pilot channel design improves network bandwidth performance and improves user mobility tracking. Feedback and reporting rules can be established using a particular field designator, CQI, in the preferred embodiment.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventors: Yi Song, Lai King Tee, Jun Li
  • Publication number: 20200266060
    Abstract: Devices and methods are provided for fabricating field-effect transistors having source/drain extension contacts to provide reduced parasitic resistance in electrical paths between source/drain layers and active channel layers surrounded by gate structures of the field-effect transistor devices. For example, in a nanosheet field-effect transistor device having embedded gate sidewall spacers which are disposed between end portions of active nanosheet channel layers and serve to insulate source/drain layers from a metal gate structure, epitaxial source/drain extension contacts are disposed between the embedded gate sidewall spacers and active nanosheet channel layers, and on sidewall surfaces of the active nanosheet channel layers. Epitaxial source/drain layers are grown starting on exposed surfaces of the epitaxial source/drain extension contacts.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Kangguo Cheng, Yi Song, Zhenxing Bi
  • Patent number: 10749011
    Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Yongan Xu, Yi Song
  • Publication number: 20200243932
    Abstract: The present disclosure provides a battery module heat management assembly, a battery pack and a vehicle. The battery module heat management assembly includes a cooling mechanism. The cooling mechanism includes: a plurality of multi-channel pipes configured to be provided at a bottom of a battery module; a first fluid collector and a second fluid collector configured to be communicated with an external cooling fluid circuit, two ends of each multi-channel pipe are respectively communicated with the first fluid collector and the second fluid collector.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Yi Song, Yanhuo Xiang
  • Publication number: 20200228837
    Abstract: The present disclosure discloses a media information processing method and apparatus. The method includes: obtaining media data that includes indication information and at least one frame of picture data. The indication information is used to indicate whether a prediction pixel corresponding to a pixel in a picture exceeds a boundary in a preset direction. The method further includes decoding the frame(s) of picture data based on the indication information. According to the media information processing method and apparatus in the present disclosure, it is possible to splice a plurality of sub-bitstreams, and required bitstreams are spliced and then are decoded, so that a plurality of sub-picture sequences can be decoded by using only a single decoder.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Yi SONG, Qingpeng XIE, Huameng FANG, Yuqun FAN
  • Publication number: 20200227720
    Abstract: The present disclosure discloses a method for forming a lead-carbon compound interface layer on a lead-based substrate, wherein the lead-based substrate has a surface, and the method includes steps of: causing an acidic solution to contact with a carbon material and a lead-containing material to form a carbon-containing plumbate precursor having an ionic lead; and reducing the ionic lead in the carbon-containing plumbate precursor to form the lead-carbon compound interface layer on the surface.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 16, 2020
    Applicant: National Formosa University
    Inventors: Shu-Huei Hsieh, Kai-Yi Song, Yi-Ren Tzeng, Ya-Wun Jan, Jing-Xiu Lin, Bo-Shun Wang, Jyun-Neng Chen
  • Patent number: 10694481
    Abstract: Described herein is a system with a first network element and a second network element. The first network element contains a processor configured to synchronize with the second network element; and maintain synchronization with the second network element. The first network element is a small cell eNB and the second network element is one of the following: a macro cell enhanced node-B (eNB); or a small cell eNB.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 23, 2020
    Assignee: BlackBerry Limited
    Inventors: Hua Xu, Shiwei Gao, Zhijun Cai, Chandra Sekhar Bontu, Yi Song, Yajun Zhu
  • Publication number: 20200194314
    Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.
    Type: Application
    Filed: December 15, 2019
    Publication date: June 18, 2020
    Inventors: Yi Song, Jay W. Strane, Eric Miller, Fee Li Lie, Richard A. Conti
  • Patent number: 10686510
    Abstract: The present invention is a method and system for supporting a beamforming antenna system in a mobile broadband communication network with an improved beam pattern, beam sweep pattern, pilot channel design with feedback and reporting rules, and control signaling design. Specifically, the improved beam pattern includes a method of supporting wireless communications in a wireless network forming at least two spatial beams within a cell segment where the at least two spatial beams are associated with different power levels, and separately, where at least two spatial beams can be moved across the cell segment according to a unique sweep pattern. The pilot channel design improves network bandwidth performance and improves user mobility tracking. Feedback and reporting rules can be established using a particular field designator, CQI, in the preferred embodiment.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Yi Song, Lai King Tee, Jun Li
  • Publication number: 20200176332
    Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
    Type: Application
    Filed: February 11, 2020
    Publication date: June 4, 2020
    Inventors: Yi Song, Veeraraghavan S. Baskar, Jay W. Strane, Ekmini Anuja De Silva
  • Patent number: 10672668
    Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Jay W. Strane, Eric Miller, Fee Li Lie, Richard A. Conti
  • Patent number: 10665514
    Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Veeraraghavan S. Baskar, Jay W. Strane, Ekmini Anuja De Silva
  • Patent number: 10658715
    Abstract: The present disclosure provides a battery module heat management assembly which comprises a cooling mechanism (1), heating films (2) and heat insulating layers (3).
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: May 19, 2020
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Yi Song, Yanhuo Xiang
  • Publication number: 20200154138
    Abstract: An image processing method includes performing horizontal division and vertical division on a longitude-latitude map or a sphere map of a to-be-processed image to obtain sub-areas of the longitude-latitude map or the sphere map, where a division location of the horizontal division is a preset latitude, a division location of the vertical division is determined by a latitude, there are at least two types of vertical division intervals in an area formed by adjacent division locations of the horizontal division, and a vertical division interval is a distance between adjacent division locations of the vertical division, and encoding images of the sub-areas.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Yi Song, Qingpeng Xie, Peiyun Di
  • Publication number: 20200135893
    Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: ZHENXING BI, Kangguo Cheng, YONGAN Xu, Yi Song
  • Publication number: 20200128543
    Abstract: A mobile station receives a downlink control structure in a first carrier, where the downlink control structure indicates that control information for the mobile station is on a second, different carrier. The mobile station decodes the control information in the second carrier, where the control information specifies resource allocation of a wireless link for the mobile station. More specifically, according to some implementations, the control channel in the first carrier specifies the resource allocation for an extended control channel in the second carrier, where the extended control channel specifies the resource allocation for traffic data of a wireless link for the mobile station.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Lai King Tee, Yi Song, Jun Li, Yuqiang Tang, Neng Wang
  • Publication number: 20200119168
    Abstract: Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Yi Song, Junli Wang, Chi-Chun Liu, Liying Jiang
  • Publication number: 20200098929
    Abstract: A method of forming a semiconductor device is provided that includes forming a first source/drain region in a supporting substrate abutting a fin structure; and forming an isolation region in the supporting substrate adjacent to a first side of the fin structure, wherein the first source/drain region is positioned on an opposing second side of the fin structure. A gate structure is formed on the channel region portion of the fin structure. In a following step, a second source/drain region on an upper surface of the fin structure. Contacts can be formed aligned to the first source/drain region and the gate structure.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Yi Song, Juntao Li, Kangguo Cheng