Abstract: A method, a computer-readable medium, and an apparatus for transport service are provided. The apparatus may receive a plurality of transport service transactions associated with a point of interest entity. For each transport service transaction, the apparatus may determine a transport service location at which the transport service transaction is executed. The apparatus may cluster the transport service locations determined for the plurality of transport service transactions. The apparatus may determine one or more candidate transport service locations for the point of interest entity based on the clustering. The apparatus may provide the one or more candidate transport service locations to a client or a service provider associated with a transport service transaction that is to be executed at the point of interest entity.

Abstract: The invention provides a semiconductor manufacturing method, which comprises providing a substrate with a photoresist layer, forming a hydrophilic film on a surface of the photoresist layer by a spin coating process, and forming a top anti-reflective coating (TARC) on the surface of the hydrophilic film.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Abstract: An electronic device includes a first substrate, a second substrate, a first circuit board, and a first layer. The first substrate includes a first bonding area. The second substrate overlapped with the first substrate. The first circuit board bonded to the first bonding area. The first layer disposed on the first circuit board, wherein a surface of the first layer away from the second substrate has a curved surface.

Abstract: An overlay mark includes a bottom overlay mark on a bottom level, a middle overlay mark on a middle level, and a top overlay mark on a top level. The bottom overlay mark, the middle overlay mark and the top overlay mark vertically overlap with one another.

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Abstract: A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.

Abstract: The invention provides a semiconductor manufacturing process, which comprises the following steps: using a computer system to define plurality of shots on a wafer range, distributing a plurality of observation points in each shot, finding out parts of incomplete shots from all of the shots, calculating the number of observation points in each incomplete shot, eliminating the incomplete shots with the number less than 3 observation points, counting all observation points in the remaining incomplete shots, and deleting a part of observation points until the total number of observation points meets a preset total number, and uniformly distributing all observation points, and performing an overlay measurement step on the remaining observation points to generate an offset vector map.

Abstract: Methods for making laser-marked packaged surface acoustic wave devices are provided. The method may include directly marking a surface of a piezoelectric substrate, where the opposite surface of the piezoelectric substrate includes a package structure encapsulating a surface acoustic wave device. The method may include exposing the surface of the piezoelectric substrate to light from a deep ultraviolet laser. By using a wavelength readily absorbed by the piezoelectric substrate, a relatively shallow marking may be made in the piezoelectric substrate. The markings may extend less than 1 micrometer into the piezoelectric substrate, and do not affect the structural integrity of the piezoelectric substrate or the operation of the packaged surface acoustic wave device.

Abstract: A method of removing a hard mask layer includes providing a gate. A hard mask layer covers and contacts a top surface of the gate. Two spacer structures respectively contacts two sides of the gate. Two first spacers are respectively disposed on the two spacer structures. Later, a wet etching process is performed to remove the hard mask layer and the first spacers and keep the spacer structures. An etchant is utilized in the wet etching process. A selective etching ratio of the silicon nitride to silicon oxide of the etchant is more than 90. The etchant includes Si(OH)4. A concentration of Si(OH)4.is greater than or equal to 3.95 ppm and smaller than or equal to 10 ppm.

Abstract: A manufacturing method of a resistive memory device includes the following steps. A first electrode is formed. A first metal oxide layer is formed on the first electrode, and the first metal oxide layer includes first metal atoms. A multilayer insulator structure is formed on the first metal oxide layer. A second metal oxide layer is formed on the multilayer insulator structure. The second metal oxide layer includes second metal atoms, the multilayer insulator structure includes third metal atoms, and each of the third metal atoms is identical to each of the second metal atoms. A second electrode is formed on the second metal oxide layer. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in a vertical direction, and an atomic percent of the third metal atoms in the multilayer insulator structure changes in the vertical direction.

Abstract: Packaged surface acoustic wave devices are provided. The packaged surface acoustic wave devices are relatively thin and can have a height of less than 220 micrometers. The packaged surface acoustic wave device includes a photosensitive resin over a conductive structure which may be formed by a plating process. The conductive structure may overlie a cavity-defining structure encapsulating a surface acoustic wave device, the cavity-defining structure including walls and a roof. The photosensitive resin can include a phenol resin. The photosensitive resin can be relatively thin. Edge portions of a piezoelectric substrate can be free from the photosensitive resin.

Abstract: A computing device selects new test configurations for testing software. Software under test is executed with first test configurations to generate a test result for each test configuration. Each test configuration includes a value for each test parameter where each test parameter is an input to the software under test. A predictive model is trained using each test configuration of the first test configurations in association with the test result generated for each test configuration based on an objective function value. The predictive model is executed with second test configurations to predict the test result for each test configuration of the second test configurations. Test configurations are selected from the second test configurations based on the predicted test results to define third test configurations. The software under test is executed with the defined third test configurations to generate the test result for each test configuration of the third test configurations.

Abstract: An automated computer implemented method of deduplicating point of interest of computer implemented database including: standardizing data of a pair of records, wherein equivalent words with different spelling may be normalized to a single spelling; classifying the pair of records into a category of pre-defined address categories; carrying out a category specific determination of non-duplicate and failing to determine that the pair of records may be a category specific non-duplicate; tokenizing the data of the pair of records into a pair of tokenized records; determining that core words of the pair of records are linked by computing scores of cross information and distance; and determining whether the scores pass a pre-determined threshold. An aspect of the disclosure relates to an electronic data processing system, a data processing apparatus, a non-transitory computer-readable medium, and a computer executable code for deduplicating point of interest of computer implemented database.

Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Abstract: A display device includes a display panel and a transparency control panel. The display panel includes a first bonding area. The transparency control panel is disposed below the display panel and includes a second bonding area. The first bonding area is not shielded by the transparency control panel, and the second bonding area is not shielded by the display panel.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Abstract: The invention provides a cooling system in an exposure machine, which comprises an exposure machine for performing an exposure process of a semiconductor, at least one water storage tank, wherein the water storage tank is filled with cooling water for cooling some components of the exposure machine, a water inlet valve and a water outlet valve, which are connected with the water storage tank, and an automatic controller for controlling the water inlet valve and the water outlet valve to keep the cooling water in the water storage tank at a certain water level.

Abstract: A resistive random access memory includes a bottom electrode, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, and a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer.