Abstract: The invention provides a semiconductor testkey, which comprises a testkey on a substrate, the testkey comprises a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.

Abstract: A device for recognizing wafer identification number with automatically turning on and off recognizing function comprises a base, a support frame, a light source, a plurality of image capturing units, an image recognition unit and a control unit. The base comprises a wafer boat placing portion and a first switch disposed on the wafer boat placing portion. The light source and the image capturing units are disposed on the support frame. The control unit is electrically connected to the first switch, the light source, the image capturing units and the image recognition unit. As such, the device for recognizing wafer identification number with automatically turning on and off recognizing function can automatically turn on and off the light source, the image capturing units, and the image recognition unit, therefore the operation is very easy and convenience.

Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Abstract: A testkey structure for semiconductor device includes a substrate, a gate structure disposed on the substrate, and a plurality of first dummy gate structures disposed on the substrate and arranged around the gate structure. A bottom surface of the gate structure is lower than bottom surfaces of the first dummy gate structures. A top surface of the gate structure is flush with top surfaces of the first dummy gate structures.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.

Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Abstract: The invention provides a deposition machine, which comprises a chamber, a first pipeline and a second pipeline, wherein one end of the first pipeline and one end of the second pipeline are connected to the chamber, and a part of the second pipeline passes through a sidewall of the first pipeline and extends into the interior of the first pipeline. The deposition machine has the advantages of reducing the risk of pipeline blockage.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.

Abstract: A semiconductor device includes a resistor disposed on a second etching stop layer in the resistor forming region. A fourth interlayer dielectric layer covers the resistor and the second etch stop layer. A first via is located in the fourth interlayer dielectric layer and is electrically connected to a terminal of the resistor. By forming the resistor in BEOL process, the problem of the contact stop depth difference that affects the process window and causes the reduced yield can be improved.

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.

Abstract: An apparatus for thermally processing a substrate includes a substrate support for holding the substrate and lamps disposed above the substrate support. The lamps are grouped into concentric lamp zones including a center zone comprised of a center lamp and peripheral lamps surrounding the center lamp. A center sleeve is coupled to the center lamp and peripheral sleeves are coupled to the peripheral lamps, respectively, for directing radiated heat to the substrate during thermal processing. The center sleeve has a higher surface roughness than that of the peripheral sleeves.

Abstract: A cleaning process of wafer polishing pad, the process includes providing a wafer polishing pad, performing a planarization process with the wafer polishing pad, leaving a residue on the wafer polishing pad after the planarization process, and performing a cleaning step with a cleaning nozzle to remove the residue, the cleaning nozzle comprises at least one Y-shaped pipe, one end of which is a water outlet, and the other two ends are respectively a water inlet and an air inlet, wherein a cleaning liquid flows from the water inlet to the water outlet, and a pressurized gas flows in from the air inlet.

Abstract: A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.

Abstract: The invention provides a correction and compensation method in a semiconductor manufacturing process. The method includes the following steps: providing a machine, the machine is at least used for exposure manufacturing of a first product and a second product, performing period maintenance (PM) on the machine, recording an original offset map before and after the period maintenance of the machine is performed, the original offset map has an original exposure size, and adjusting the original exposure size of the original offset map to correspond to a first exposure size of the first product, and performing a first offset compensation correction on the first product. And adjusting the original exposure size of the original offset map to correspond to a second exposure size of the second product, and performing a second offset compensation correction on the second product.

Abstract: An apparatus and method for inferring optimal pick-up/drop-off locations for transport services use historical bookings data associated with past bookings, the past bookings having a pick-up or drop-off location within a defined geographical area. Each historical data instance for a booking includes a geographical data point recorded at a time of a pick-up/drop-off event within the geographical area. The historical data is processed to identify clusters of geographic data points having similar geographical locations. A quality indicator is determined and compared with a first threshold. If the quality indicator satisfies the first threshold, a cluster centroid for each cluster is designated as an optimal pick-up/drop-off location for the geographical area.

Abstract: A method of forming semiconductor device is disclosed. A substrate having a logic circuit region and a memory cell region is provided. A first transistor with a first gate is formed in the logic circuit region and a second transistor with a second gate is formed in the memory cell region. A stressor layer is deposited to cover the first transistor in the logic circuit region and the second transistor in the memory cell region. The first transistor and the second transistor are subjected to an annealing process under the influence of the stressor layer to recrystallize the first gate and the second gate.

Abstract: Provided is a wafer notch automated aligner, including a main body, a wafer rotation mechanism, and a wafer positioning mechanism. The main body has a wafer boat placement portion. The wafer rotation mechanism is disposed on the main body and includes a rotor, the rotor extends through the wafer boat placement portion, and an angle between an axis of the rotor and the main body is between 0° and 90°. The wafer positioning mechanism is disposed on the main body and includes a positioning member, the positioning member extends through the wafer boat placement portion, and an axis of the positioning member is parallel to the axis of the rotor. Hence, a plurality of wafers is disposed in a stepped arrangement by the inclined rotor and the inclined positioning member, and the wafer notch automated aligner can rotate wafers, align notches, and identify wafer identifications.

Abstract: A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.

Abstract: A display device, characterized in that the display device includes a first panel having a first side and a first light shielding layer at a periphery of the first panel, wherein the first light shielding layer has a first edge departing away from the first side; and a second panel, disposed on the first panel, and having a second side adjacent to the first side; wherein the second panel includes a second light shielding layer at a periphery of the second panel; and the second light shielding layer has a second edge departing away from the second side. Wherein a first width is measured from the first side to the first edge along a direction, a second width is measured from the second side to the second edge along the direction, the second width is greater than the first width, and the direction is vertical to the first side.

Abstract: A resistive memory device includes a stacked structure and a copper via conductor structure. The stacked structure includes a first electrode, a second electrode, and a variable resistance layer. The second electrode is disposed above the first electrode in a vertical direction, and the variable resistance layer is disposed between the first electrode and the second electrode in the vertical direction. The copper via conductor structure is disposed under the stacked structure. The first electrode includes a tantalum nitride layer directly connected with the copper via conductor structure.