Patents by Inventor Yi-Ting Wang
Yi-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12221006Abstract: Management methods and systems for energy and charging requests of an electric vehicle charging field are provided. First charging data corresponding to at least one first charging operation is received by a server from each of electric vehicle charging stations in a charging field via a network during a first predetermined period, wherein the charging data includes at least a charging start time, a charging period, and an output power. According to the first charging data corresponding to the at least one first charging operation received from each of the electric vehicle charging stations during the first predetermined period, the server generates an energy prediction data of the charging field in a second predetermined period, wherein the energy prediction data includes at least an energy consumption estimation of the charging field at a specific time point.Type: GrantFiled: January 19, 2022Date of Patent: February 11, 2025Assignee: NOODOE GROUP INC.Inventors: John C. Wang, Yu-Ting Liou, Yi-An Hou, Chun-Hung Kung
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Patent number: 12170202Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: January 2, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Publication number: 20240363350Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
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Publication number: 20240145494Abstract: An image sensor structure including a substrate, a first pixel structure, a second pixel structure, a dielectric layer, and a conductive layer stack is provided. The first pixel structure includes a first light sensing device. The second pixel structure includes a second light sensing device. The conductive layer stack includes conductive layers. The conductive layer stack has a first opening and a second opening. The first opening is located directly above the first light sensing device and passes through the conductive layers. The second opening is located directly above the second light sensing device and passes through the conductive layers. The second minimum width of the second opening is smaller than the first minimum width of the first opening. The luminous flux of the second pixel structure is different from the luminous flux of the first pixel structure.Type: ApplicationFiled: November 22, 2022Publication date: May 2, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ju-Sheng Lu, Yi-Ting Wang, Ming-Chan Liu
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Patent number: 11829216Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine a temperature value associated with a discrete graphics processing unit (dGPU); if the temperature value is below a threshold temperature value: configure an information handling system (IHS) to utilize the dGPU for processing graphics workloads of the IHS; disable an integrated graphics processing unit (iGPU) from processing any of the graphics workloads; and provide an amount of power utilized by the iGPU to a processor of the IHS; and if the temperature value is not below the threshold temperature value: determine that the iGPU is disabled; configure the IHS to utilize the iGPU for processing a portion of the graphics workloads; and enable the iGPU to process the portion of the graphics workloads; and remove the amount of power utilized by the iGPU from the at least one processor.Type: GrantFiled: March 22, 2021Date of Patent: November 28, 2023Assignee: Dell Products L.P.Inventors: Thomas Alexander Shows, Yi-Ting Wang
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Publication number: 20230282482Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.Type: ApplicationFiled: June 4, 2022Publication date: September 7, 2023Inventors: Tsung-Han Shen, Kevin Chang, Yu-Ming Li, Chih-Hsiang Fan, Yi-Ting Wang, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
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Publication number: 20230141521Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: January 2, 2023Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 11545363Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 21, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 11530133Abstract: A method for recovering lithium is provided. The method includes the following steps. A lithium-containing solution is provided. A manganese oxide adsorbent is immersed in the lithium-containing solution, and a reducing agent is added to carry out an adsorption reaction, and the manganese oxide adsorbent is immersed in a solution containing an oxidizing agent to carry out a desorption reaction.Type: GrantFiled: August 7, 2020Date of Patent: December 20, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Li-Ching Chung, Guan-You Lin, Yi Ting Wang, Chun-Chi Lee, Tzu Yu Cheng, Shing-Der Chen, Kuan-Foo Chang, Hsin Shao
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Patent number: 11500012Abstract: A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards.Type: GrantFiled: October 23, 2020Date of Patent: November 15, 2022Assignee: KING YUAN ELECTRONICS CO., LTD.Inventors: Chia-Hung Tsai, Kuo-Jung Wu, Hsing-Yueh Liang, Po-Wei Liao, Yi-Ting Wang
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Publication number: 20220300050Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine a temperature value associated with a discrete graphics processing unit (dGPU); if the temperature value is below a threshold temperature value: configure an information handling system (IHS) to utilize the dGPU for processing graphics workloads of the IHS; disable an integrated graphics processing unit (iGPU) from processing any of the graphics workloads; and provide an amount of power utilized by the iGPU to a processor of the IHS; and if the temperature value is not below the threshold temperature value: determine that the iGPU is disabled; configure the IHS to utilize the iGPU for processing a portion of the graphics workloads; and enable the iGPU to process the portion of the graphics workloads; and remove the amount of power utilized by the iGPU from the at least one processor.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Inventors: Thomas Alexander Shows, Yi-Ting Wang
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Patent number: 11415435Abstract: An encoder and a signal processing method are disclosed. The method includes: receiving an analog signal, and generating a filtered analog signal by an analog filter according to the input signal and a first frequency indication signal; generating a digital signal by an analog-to-digital converter according to the filtered analog signal; generating a filtered digital signal by a digital filter according to the digital signal and a second frequency indication signal; generating a seventh signal and an eighth signal by a dynamic offset calibration unit according to the filtered digital signal and a period indication signal; and generating a position information by a position detection unit according to the seventh signal and the eighth signal. The first frequency indication signal, the second frequency indication signal and the period indication signal are generated by a frequency generation module according to the filtered analog signal or the digital signal.Type: GrantFiled: June 30, 2020Date of Patent: August 16, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsan-Huang Chen, Yu-Chen Lee, Chung-Lin Tseng, Jyun-Liang Lai, Yi-Ting Wang
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Publication number: 20220208984Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.Type: ApplicationFiled: March 21, 2022Publication date: June 30, 2022Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
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Publication number: 20220175729Abstract: The present invention provides a method for treating cancer, the method including the step of: administering a therapeutically effective concentration of chlorophyllide to a subject in need thereof. The present invention further provides a method for treating cancer, the method including the step of: administering a composition to a subject in need thereof, wherein the composition includes: a therapeutically effective concentration of chlorophyllide and a therapeutically effective concentration of anthracycline.Type: ApplicationFiled: November 30, 2021Publication date: June 9, 2022Inventors: Chih-Hui YANG, Jei-Fu SHAW, Yi-Ting WANG, Ting-Yu HUANG, Mi-Hsueh TAI, Pei-Han SHIH, Ru-Han SIE
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Patent number: 11282938Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.Type: GrantFiled: July 1, 2019Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
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Publication number: 20220043052Abstract: A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards.Type: ApplicationFiled: October 23, 2020Publication date: February 10, 2022Inventors: Chia-Hung TSAI, Kuo-Jung WU, Hsing-Yueh LIANG, Po-Wei LIAO, Yi-Ting WANG
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Publication number: 20210199468Abstract: An encoder and a signal processing method are disclosed. The method includes: receiving an analog signal, and generating a filtered analog signal by an analog filter according to the input signal and a first frequency indication signal; generating a digital signal by an analog-to-digital converter according to the filtered analog signal; generating a filtered digital signal by a digital filter according to the digital signal and a second frequency indication signal; generating a seventh signal and an eighth signal by a dynamic offset calibration unit according to the filtered digital signal and a period indication signal; and generating a position information by a position detection unit according to the seventh signal and the eighth signal. The first frequency indication signal, the second frequency indication signal and the period indication signal are generated by a frequency generation module according to the filtered analog signal or the digital signal.Type: ApplicationFiled: June 30, 2020Publication date: July 1, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsan-Huang CHEN, Yu-Chen LEE, Chung-Lin TSENG, Jyun-Liang LAI, Yi-Ting WANG
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Publication number: 20210188652Abstract: A method for recovering lithium is provided. The method includes the following steps. A lithium-containing solution is provided. A manganese oxide adsorbent is immersed in the lithium-containing solution, and a reducing agent is added to carry out an adsorption reaction, and the manganese oxide adsorbent is immersed in a solution containing an oxidizing agent to carry out a desorption reaction.Type: ApplicationFiled: August 7, 2020Publication date: June 24, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Li-Ching Chung, Guan-You Lin, Yi Ting Wang, Chun-Chi Lee, Tzu Yu Cheng, Shing-Der Chen, Kuan-Foo Chang, Hsin Shao
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Publication number: 20210111027Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
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Patent number: 10872769Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 30, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang