Patents by Inventor Yi-Ting Wang

Yi-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11282938
    Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
  • Publication number: 20220043052
    Abstract: A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 10, 2022
    Inventors: Chia-Hung TSAI, Kuo-Jung WU, Hsing-Yueh LIANG, Po-Wei LIAO, Yi-Ting WANG
  • Publication number: 20210199468
    Abstract: An encoder and a signal processing method are disclosed. The method includes: receiving an analog signal, and generating a filtered analog signal by an analog filter according to the input signal and a first frequency indication signal; generating a digital signal by an analog-to-digital converter according to the filtered analog signal; generating a filtered digital signal by a digital filter according to the digital signal and a second frequency indication signal; generating a seventh signal and an eighth signal by a dynamic offset calibration unit according to the filtered digital signal and a period indication signal; and generating a position information by a position detection unit according to the seventh signal and the eighth signal. The first frequency indication signal, the second frequency indication signal and the period indication signal are generated by a frequency generation module according to the filtered analog signal or the digital signal.
    Type: Application
    Filed: June 30, 2020
    Publication date: July 1, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsan-Huang CHEN, Yu-Chen LEE, Chung-Lin TSENG, Jyun-Liang LAI, Yi-Ting WANG
  • Publication number: 20210188652
    Abstract: A method for recovering lithium is provided. The method includes the following steps. A lithium-containing solution is provided. A manganese oxide adsorbent is immersed in the lithium-containing solution, and a reducing agent is added to carry out an adsorption reaction, and the manganese oxide adsorbent is immersed in a solution containing an oxidizing agent to carry out a desorption reaction.
    Type: Application
    Filed: August 7, 2020
    Publication date: June 24, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Ching Chung, Guan-You Lin, Yi Ting Wang, Chun-Chi Lee, Tzu Yu Cheng, Shing-Der Chen, Kuan-Foo Chang, Hsin Shao
  • Publication number: 20210111027
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Patent number: 10872769
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20200355697
    Abstract: Provided is a method for identifying proteins capable of increasing the number of identified proteins contained in a target sample derived from blood. A protein contained in the target sample derived from blood is fragmented, and a protein contained in an having less bias in a quantity ratio of proteins than the target sample is fragmented, and the fragmented proteins are mixed (Steps S101 to S103). In this manner, the mixed sample in which the bias in a quantity ratio of proteins is less than that of the target sample is generated. By performing MS/MS measurement using the generated mixed sample (Step S107), an MS/MS spectrum of a peak derived from a protein contained in a small amount in the target sample can be prevented from being missed. Accordingly, the number of identified proteins contained in the target sample derived from blood can be increased.
    Type: Application
    Filed: January 9, 2018
    Publication date: November 12, 2020
    Applicant: SHIMADZU CORPORATION
    Inventors: Kazuhiro SONOMURA, Taka-Aki SATO, Fumihiko MATSUDA, Yi-Ting WANG, Yasushi ISHIHAMA, Chia-Feng TSAI
  • Publication number: 20200135471
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Publication number: 20200105895
    Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
  • Patent number: 10535523
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20190195757
    Abstract: Provided is a detection method for heavy metal ions that includes the following steps. A waste water is flowed through an ion-imprinted polymer tube for adsorbing at least two kinds of target heavy metal ions. The ion-imprinted polymer tube is rinsed to remove a non-target object from the ion-imprinted polymer tube. The target heavy metal ions in the ion-imprinted polymer tube are desorbed by using an acid liquid. An electrochemical method is performed to detect concentrations of the target heavy metal ions.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Chi Lee, Shu-Kang Hsu, Min-Shan Wu, Yi-Ting Wang, Ting-Ting Chang, Kuan-Foo Chang
  • Patent number: 10271821
    Abstract: A method of ultrasound imaging and a corresponding ultrasound scanner are provided. The method includes the steps of receiving an echo signal induced by an ultrasonic plane wave transmission from a transducer of an ultrasound scanner, resampling the echo signal in time domain and/or space domain, performing a spectrum zooming on a band of interest (BOI) of an input signal, performing a Fourier transform on a result of the spectrum zooming, and generating an ultrasound image based on a result of the Fourier transform. The input signal is generated based on the resampling of the echo signal.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 30, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Lien Ho, Yi-Ting Wang, Ren-Jr Chen, Chu-Yu Huang
  • Patent number: 10157975
    Abstract: A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu Ma, Chia-Hui Chen, Yi-Ting Wang
  • Patent number: 9967886
    Abstract: The present disclosure proposes a hierarchical beamforming method and a base station and a user equipment using the same. The method includes following steps. A network entry procedure is performed via a plurality of coarse beams by using a superframe header of a superframe corresponding to each of the coarse beams. In response to a success message associated with the network entry procedure being received, a network entry done message is transmitted by using a preferred coarse beam among the coarse beams. A user equipment (UE) connection is performed via a plurality of fine beams within a direction range of the preferred coarse beam, so as to determine a preferred fine beam by using a frame header of a basic frame corresponding to each of the fine beams, and perform a data packet transmission by using a packet transmission block of the basic frame corresponding to the preferred fine beam.
    Type: Grant
    Filed: November 26, 2015
    Date of Patent: May 8, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Lien Ho, Ren-Jr Chen, Yi-Ting Wang, Wen-Chiang Chen, Pang-An Ting
  • Patent number: 9864059
    Abstract: According to an exemplary embodiment, an ultrasound apparatus for beamforming with a plane wave transmission may comprise a transceiver connected to a transducer array having at least one transducer element, and at least one processor. The transceiver transmits at least one substantially planar ultrasonic wave into a target region at one or more angles relative to the transducer array, and receives one or more signals responsive from the transducer array. The at least one processor applies a fast Fourier transform (FFT) to the one or more signals from each of the at least one transducer element and calculates at least one frequency within a frequency region, and applies an inverse FFT to at least one produced frequency data.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: January 9, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chu-Yu Huang, Chir-Weei Chang, Kuo-Tung Tiao, Wen-Hung Cheng, Hsin-Yueh Sung, Ren-Jr Chen, Chung-Lien Ho, Yi-Ting Wang
  • Patent number: 9856346
    Abstract: A method of forming a lignin-based biomass epoxy resin is provided, which includes: (a) mixing a lignin, an acid anhydride compound, and a solvent to react for forming a first intermediate product, (b) reacting the first intermediate compound with a first polyol to form a second intermediate compound, and (c) reacting the second intermediate compound with an epoxy compound to form a lignin-based biomass epoxy resin.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: January 2, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuung-Ching Sheen, Yi-Ting Wang, Su-Mei Chen Wei, Yi-Che Su, Wen-Pin Chuang
  • Publication number: 20170207295
    Abstract: A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.
    Type: Application
    Filed: April 4, 2017
    Publication date: July 20, 2017
    Inventors: Wei-Yu MA, Chia-Hui CHEN, Yi-Ting WANG
  • Patent number: 9640605
    Abstract: A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: May 2, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu Ma, Chia-Hui Chen, Yi-Ting Wang
  • Patent number: 9507897
    Abstract: One or more circuit arrangements and techniques for modeling are provided. In some embodiments, a circuit arrangement includes at least one of a first current source, a second current source, a first diode, a second diode, and a switching component. In some embodiments, the switching component includes a bipolar junction transistor (BJT). In some embodiments, the circuit arrangement is integrated into a metal oxide semiconductor (MOS) device. When the circuit arrangement is integrated into a MOS device, at least one of a substrate current leakage, a junction breakdown, or a diode reverse recovery (DRR) effect is predictable for the MOS device.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Ting Wang, Chia-Ying Lin, Run-Ci Gao, Hung-Han Lin, Chia-Chi Ho, Chung-Shi Chiang
  • Publication number: 20160293689
    Abstract: A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 6, 2016
    Inventors: Wei-Yu MA, Chia-Hui CHEN, Yi-Ting WANG