Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Abstract: A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrated contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.

Abstract: A method for fabricating a semiconductor structure includes the following steps. Decomposing a layout to first connection patterns and second connection patterns alternatively arranged with each other, where a to-be-split pattern is disposed between the first connection pattern and the second connection pattern; splitting the to-be-split pattern into a cutting portion and a counterpart cutting portion; forming a first photomask having a layout constructed by the first connection pattern and the cutting portion; forming a second photomask having a layout constructed by the second connection pattern and the counterpart cutting portion; transferring layouts of the first and second photomasks to a target layer to form connection patterns and a merged pattern, where the contour of the merged pattern is defined by the cutting portion and the counterpart cutting portion, and each end surface of the merged pattern comprises a recessed region and a protruded region.

Abstract: A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.

Abstract: A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad (500) is arranged lateral to a first contact pad (420) in an interconnect structure (400). As a result, during fabrication of the interconnect structure (400), the first contact pad (420) will not be present alone in a large bland area, due to the presence of the second contact pad (500). Thus, a pattern feature for the first contact pad (420) will not be over-resolved, increasing formation accuracy of the first contact pad (420) and thus guaranteeing good electrical transmission performance of the resulting interconnect structure (400).

Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Abstract: A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.

Abstract: The invention provides a contact plug structure. The contact plug structure comprises a substrate and a dielectric layer, and a first contact hole located in the dielectric layer and penetrating into the substrate, the first contact hole has a first through hole portion located in the dielectric layer and a first groove located in the substrate, and the first through hole portion is communicated with the first groove, the maximum width of the first groove is larger than that of the first through hole portion in the direction parallel to the substrate surface. A barrier layer at least partially covering the sidewall of the first groove. A conductive pad layer is located on the bottom surface of the first groove. The conductive core layer is arranged on the conductive pad layer, and the barrier layer wraps the conductive pad layer and the conductive core layer.

Abstract: A semiconductor structure includes a substrate, a contact structure disposed on the substrate, and two first gate structures disposed on the substrate and at two sides of the first contact structure. The contact structure has a T-shaped cross-sectional profile having a first portion contacting the substrate and a second portion disposed on the first portion. A top surface of the second portion of the contact structure is flush with top surfaces of the two first gate structures.

Abstract: A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.