Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

Abstract: A pixel structure of display panel includes a first thin film transistor device, a second thin film transistor device, a first passivation layer, a common electrode, a second passivation layer, a first pixel electrode and a second pixel electrode. The first passivation layer has a first opening partially exposing a first drain electrode of the first thin film transistor device and a second drain electrode of the second thin film transistor device. The common electrode has a second opening partially exposing the first drain electrode and the second drain electrode. The second passivation layer has a third opening partially exposing the first drain electrode and the second drain electrode. The first pixel electrode is electrically connected to the first drain electrode through the third opening, the second opening and the first opening, and the second pixel electrode is electrically connected to the second drain electrode through the third opening, the second opening and the first opening.

Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract: A pixel structure of display panel includes a first thin film transistor device, a second thin film transistor device, a first passivation layer, a common electrode, a second passivation layer, a first pixel electrode and a second pixel electrode. The first passivation layer has a first opening partially exposing a first drain electrode of the first thin film transistor device and a second drain electrode of the second thin film transistor device. The common electrode has a second opening partially exposing the first drain electrode and the second drain electrode. The second passivation layer has a third opening partially exposing the first drain electrode and the second drain electrode. The first pixel electrode is electrically connected to the first drain electrode through the third opening, the second opening and the first opening, and the second pixel electrode is electrically connected to the second drain electrode through the third opening, the second opening and the first opening.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.

Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.

Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract: For producing an inter-layer conductive structure of a circuit board, an insulating layer, a first conductive layer, a second conductive layer and an electric contact material are provided, wherein the insulating layer includes at least a conductive hole therein. The electric contact material is inserted into the conductive hole of the insulating layer to form a conductive plug, and the first and second conductive layers are laminated to opposite surfaces of the insulating layer, respectively. After lamination, the conductive plug has two ends thereof in electric contact with the first conductive layer and the second conductive layer, respectively.

Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.

Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract: A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.