Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.

Abstract: A chamber door, such as an etch chamber door may be heated during etch processing to, e.g., prevent etching by-products from adhering to the etch chamber door. Such heating of the etch chamber door, however, can impact the processing parameters and result in non-uniform processing, such as non-uniform etching characteristics across a semiconductor wafer, for instance. An insulator, such as an insulating film covering surfaces of the heated door, can reduce or eliminate transmission of heat from the door to a work piece such as a semiconductor wafer and this reduce or eliminate the non-uniformity of the process results.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element has a lower portion and an upper portion, the lower portion has a substantially uniform width. The upper portion becomes wider along a direction from a top of the spacer element towards the lower portion, and a bottom of the upper portion is higher than a top of the gate stack. The semiconductor device also includes a dielectric layer surrounding the gate stack and the spacer element. The semiconductor device further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate.

Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.

Abstract: An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: Certain aspects direct to systems and methods for providing an intuitive user interface (UI) for device or vendor independent network switch management via a management controller. The management controller is communicatively connected to a network switch through a Simple Network Management Protocol (SNMP) interface. The management controller provides a web UI. When a remote computing device request the web UI, the management controller sends the web UI to the remote computing device. Thus, a user at the remote computing device may upload the parsed information of the MIB file to the management controller through the UI. The management controller then processes the parsed information of the MIB file, and displays the processed parsed information in a hierarchical organization through the UI. Then the management controller establishes a communication between the management controller and the network switch through the SNMP interface based on the parsed information of the MIB file.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.

Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.

Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.

Abstract: Systems and methods for providing and supporting multiple Intelligent Platform Management Interface (IPMI) serial over local area network (SOL) sessions in a management controller. The system includes a management controller used to manage multiple nodes, and at least one remote computing device connected to the management controller via a local area network (LAN). In operation, the management controller configures multiple serial ports for the nodes, so the management controller is communicatively connectable to each of the nodes respectively via one of the serial ports. When the management controller receives a SOL request from the remote computing device to establish a SOL session to access a specific node, the management controller may accordingly establish the SOL session between the specific node and the remote computing device sending the SOL request. Thus, the management controller may support multiple SOL sessions, and may store information of each of the SOL sessions independently.