Patents by Inventor Yi-Wen Chiu

Yi-Wen Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160336354
    Abstract: A display panel includes an active device array substrate, an opposite substrate, a display medium and a sealant. The active device array substrate includes a substrate, an active device array, a passivation layer and an enhancement layer. A material of the enhancement layer is different from a material of the passivation layer. The opposite substrate is disposed opposite to the active device array substrate. The display medium is disposed between the active device array substrate and the opposite substrate. The sealant is disposed between the active device array substrate and the opposite substrate and surrounds the display medium. An end of the sealant directly contacts the enhancement layer, and a material of the enhancement layer is the same as a material of the sealant.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 17, 2016
    Inventors: Yi-Wen Chiu, Yen-Wei Liu, Ji-Yi Chiou, Ming-Hsiang Lai, Sheng-Fa Liu, Ching-Yu Huang, Yi-Fan Niu
  • Publication number: 20160052250
    Abstract: A frit encapsulation apparatus includes a carriage, a mask, a laser light source and a pressure element. The carriage is disposed over a first substrate. The mask is disposed in the carriage and has a light-transmitting region. The laser light source is disposed in the carriage and over the mask and is configured to provide laser light through the light-transmitting region of the mask and the first substrate therebeneath to heat the frit beneath the first substrate. The pressure element is disposed beneath the carriage and is configured to provide a pressure to the first substrate, such that the first substrate is adhered to a second substrate by the heated frit, in which the pressure element is not overlapped with a vertical projection of the light-transmitting region on the first substrate.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 25, 2016
    Inventors: Yi-Wen Chiu, Sheng-Fa Liu, Ji-Yi Chiou, Ching-Yu Huang, Ming-Hsiang Lai, Yen-Wei Liu
  • Patent number: 8975871
    Abstract: A power management method and an electronic system using the same are provided. The electronic system includes a display device and an auxiliary device, and has dual batteries and two subsystems. By detection and control mechanisms of the subsystems, the electronic system may allow the display device to maintain in a full power state, in the case where the external power is available or the power of the auxiliary device is sufficient. On the other hand, the auxiliary device may apply to the display device, such as a notebook computer, and the battery time may also be extended since the computer has two batteries.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 10, 2015
    Assignee: ASUSTeK Computer Inc.
    Inventors: Chih-Wan Hsu, Nung-Te Huang, Yi-Wen Chiu, Hsi-Ho Hsu
  • Publication number: 20140331067
    Abstract: A portable electronic device is provided. The portable electronic device includes a host, a power adapter and a signal transmission interface. The host generates state information according to present operating state, and the power adapter is used to provide a voltage to the host. The power adapter receives the state information of the host via the signal transmission interface, and adjusts the output voltage according to the state information. By transmitting information between the host and the power adapter, the power adapter can be adjusted according to the operating state of the host. Moreover, the host can adjust the operating state according to the specification information of the power adapter. Consequently, the power consuming of the portable electronic device has best efficiency thus to reduce carbon emission.
    Type: Application
    Filed: April 29, 2014
    Publication date: November 6, 2014
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yao-Hwa Chen, Yi-Wen Chiu, Sheng-Wei Hsiao
  • Patent number: 8667307
    Abstract: A power control circuit and a power control method applied to a computer system are disclosed. A regulator receives a first voltage, the regulator converting the first voltage to an embedded controller voltage when the regulator is enabled. A detecting and controlling circuit receives the first voltage and the button signal, and the regulator is enabled when the detecting and controlling circuit detects the button signal. An embedded controller connects to the regulator for receiving the embedded controller voltage and outputting the plurality of power control signals. The embedded controller sends a power on signal to the detecting and controlling circuit to keep the regulator enabled.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 4, 2014
    Assignee: ASUSTeK Computer Inc.
    Inventor: Yi-Wen Chiu
  • Publication number: 20120299530
    Abstract: A power management method and an electronic system using the same are provided. The electronic system includes a display device and an auxiliary device, and has dual batteries and two subsystems. By detection and control mechanisms of the subsystems, the electronic system may allow the display device to maintain in a full power state, in the case where the external power is available or the power of the auxiliary device is sufficient. On the other hand, the auxiliary device may apply to the display device, such as a notebook computer, and the battery time may also be extended since the computer has two batteries.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chih-Wan Hsu, Nung-Te Huang, Yi-Wen Chiu, Hsi-Ho Hsu
  • Patent number: 7859325
    Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: December 28, 2010
    Assignee: ASUSTeK Computer Inc.
    Inventors: Yi-Wen Chiu, Chih-Wan Hsu, Hsi-Ho Hsu
  • Publication number: 20100293396
    Abstract: A power control circuit and a power control method applied to a computer system are disclosed. A regulator receives a first voltage, the regulator converting the first voltage to an embedded controller voltage when the regulator is enabled. A detecting and controlling circuit receives the first voltage and the button signal, and the regulator is enabled when the detecting and controlling circuit detects the button signal. An embedded controller connects to the regulator for receiving the embedded controller voltage and outputting the plurality of power control signals. The embedded controller sends a power on signal to the detecting and controlling circuit to keep the regulator enabled.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 18, 2010
    Applicant: ASUSTeK COMPUTER INC.
    Inventor: Yi-Wen Chiu
  • Publication number: 20100257383
    Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.
    Type: Application
    Filed: June 15, 2010
    Publication date: October 7, 2010
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Yi-Wen Chiu, Chih-Wan Hsu, Hsi-Ho Hsu
  • Patent number: 7764111
    Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: July 27, 2010
    Assignee: Asustek Computer Inc.
    Inventors: Yi-Wen Chiu, Chih-Wan Hsu, Hsi-Ho Hsu
  • Publication number: 20090167423
    Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.
    Type: Application
    Filed: September 25, 2008
    Publication date: July 2, 2009
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Yi-Wen Chiu, Chih-Wan Hsu, Hsi-Ho Hsu
  • Publication number: 20090156050
    Abstract: A power detection jack can be connected with a plurality of power output jacks respectively to receive different power levels. Each of the power output jacks has a first insulation element, and the lengths of the first insulation elements are different from each other. The power detection jack includes a first electrode, a second electrode and a power detection element. The first electrode is disposed inside the power detection jack. The second electrode is disposed outside the power detection jack. The power detection element is disposed between the first electrode and the second electrode. When the power detection jack is connected with one of the power output jacks, the power level provided by the power output jack is determined according to a connection state of the power detection element and the first insulation element.
    Type: Application
    Filed: September 9, 2008
    Publication date: June 18, 2009
    Inventors: Yu-Cheng SHEN, Yi-Wen Chiu, Min-Hua Hsu