Abstract: A power control circuit and a power control method applied to a computer system are disclosed. A regulator receives a first voltage, the regulator converting the first voltage to an embedded controller voltage when the regulator is enabled. A detecting and controlling circuit receives the first voltage and the button signal, and the regulator is enabled when the detecting and controlling circuit detects the button signal. An embedded controller connects to the regulator for receiving the embedded controller voltage and outputting the plurality of power control signals. The embedded controller sends a power on signal to the detecting and controlling circuit to keep the regulator enabled.

Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.

Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.

Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.

Abstract: A power detection jack can be connected with a plurality of power output jacks respectively to receive different power levels. Each of the power output jacks has a first insulation element, and the lengths of the first insulation elements are different from each other. The power detection jack includes a first electrode, a second electrode and a power detection element. The first electrode is disposed inside the power detection jack. The second electrode is disposed outside the power detection jack. The power detection element is disposed between the first electrode and the second electrode. When the power detection jack is connected with one of the power output jacks, the power level provided by the power output jack is determined according to a connection state of the power detection element and the first insulation element.