Abstract: A light-emitting device is provided. The light-emitting device comprises: an epitaxial structure comprising a first DBR stack, a light-emitting stack and a second DBR stack and a contact layer in sequence; an electrode on the epitaxial structure; a current blocking layer between the contact layer and the electrode; a first opening formed in the current blocking layer; and a second opening formed in the electrode and within the first opening; wherein a part of the electrode fills in the first opening and contacts the contact layer.

Abstract: A light-emitting device is provided. The light-emitting device is configured to emit a radiation and comprises: a substrate; an epitaxial structure on the substrate and comprising a first DBR stack, a light-emitting stack and a second DBR stack and a contact layer in sequence; an electrode; a current blocking layer between the contact layer and the electrode; a first opening formed in the current blocking layer; and a second opening formed in the electrode and within the first opening; wherein a part of the electrode fills in the first opening and contacts the contact layer; and the light-emitting device is devoid of an oxidized layer and an ion implanted layer in the second DBR stack.

Abstract: A light-emitting device is provided. The light-emitting device is configured to emit a radiation and comprises: a substrate; an epitaxial structure on the substrate and comprising a first DBR stack, a light-emitting stack and a second DBR stack and a contact layer in sequence; an electrode; a current blocking layer between the contact layer and the electrode; a first opening formed in the current blocking layer; and a second opening formed in the electrode and within the first opening; wherein a part of the electrode fills in the first opening and contacts the contact layer; and the light-emitting device is devoid of an oxidized layer and an ion implanted layer in the second DBR stack.

Abstract: A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray.

Abstract: This disclosure discloses a light-emitting chip comprises: a light-emitting stack, having a side wall, comprising an active layer emitting light; and a light-absorbing layer having a first portion surrounding the side wall and being configured to absorb 50% light toward the light-absorbing layer.

Abstract: This disclosure discloses a light-emitting chip comprises: a light-emitting stack, having a side wall, comprising an active layer emitting light; and a light-absorbing layer having a first portion surrounding the side wall and being configured to absorb 50% light toward the light-absorbing layer.

Abstract: A resonant converter with power factor correction includes a power-obtaining circuit, an energy-storage element and an energy-transferred circuit. The power-obtaining circuit is used for receiving an input line voltage. The energy-storage element is coupled between the power-obtaining circuit and the energy-transferred circuit. The energy-transferred circuit is used for generating an output power. In a first time period, based on a first control signal, the energy-storage element and the power-obtaining circuit operate a soft switching so that the energy-storage element is charged to obtain the input line power and generate an energy-storage voltage. In a second time period, based on a second control signal, the energy-storage element and the energy-transferred circuit operate a soft switching so that the energy-storage element is discharged to make the energy-storage voltage converted into the output power.

Abstract: This disclosure discloses a light-emitting chip comprises: a light-emitting stack, having a side wall, comprising an active layer emitting light; and a light-absorbing layer having a first portion surrounding the side wall and being configured to absorb 50% light toward the light-absorbing layer.

Abstract: A common-core power factor correction resonant converter includes an energy-transforming circuit. The energy-transforming circuit receives an input line voltage and generates an output power. The energy-transforming circuit includes a coupling inductor and a charge-storage capacitor. The coupling inductor and the charge-storage capacitor are charged by the input line voltage in response to a control signal, so as to generate a charge-storage capacitor voltage. When the charge-storage capacitor voltage is charged to a preset voltage level, the coupling inductor and the charge-storage capacitor are discharged according to the control signal. Then, the energy in the coupling inductor and the charge-storage capacitor is transformed to the output load and provide the output voltage or current regulation.

Abstract: This disclosure discloses a light-emitting chip comprises: a light-emitting stack, having a side wall, comprising an active layer emitting light; and a light-absorbing layer having a first portion surrounding the side wall and being configured to absorb 50% light toward the light-absorbing layer.

Abstract: The disclosure provides a method for controlling an equivalent resistance of a converter. The method includes receiving a power source input signal, generating a first control signal according to a voltage level and a state of the power source input signal to adjust an equivalent resistance of the voltage conversion module and cause the voltage conversion module to operate in the damper mode or the converter mode, when the voltage conversion module operates in the converter mode converting the power source input signal to an output signal, and when the voltage conversion module operates in the damper mode detecting the voltage level or the current level of the power source input signal, and adjusting the equivalent resistance so that the voltage conversion module could operate in the bleeder mode or the converter mode to convert the power source input signal to the output signal.

Abstract: A common-core power factor correction resonant converter includes an energy-transforming circuit. The energy-transforming circuit receives an input line voltage and generates an output power. The energy-transforming circuit includes a coupling inductor and a charge-storage capacitor. The coupling inductor and the charge-storage capacitor are charged by the input line voltage in response to a control signal, so as to generate a charge-storage capacitor voltage. When the charge-storage capacitor voltage is charged to a preset voltage level, the coupling inductor and the charge-storage capacitor are discharged according to the control signal. Then, the energy in the coupling inductor and the charge-storage capacitor is transformed to the output load and provide the output voltage or current regulation.

Abstract: A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station.

Abstract: A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray.

Abstract: A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station.

Abstract: A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station.

Abstract: The present invention discloses a current generating apparatus for generating an output current. The current generating apparatus includes: a first current mirror; a first bias current generator for providing a first bias current, and the first bias current generator includes: a first current source for providing the first current; and a capacitive device for conducting a reference current; a second current mirror for generating a second mirror current; a second bias current generator for generating a second current; a third current source for providing a third current, wherein the second mirror current is equal to the third current; a feedback circuit; and a fourth current source for providing a fourth current, wherein the output current is outputted at an output node of the first current mirror.

Abstract: The present invention discloses a current generating apparatus for generating an output current. The current generating apparatus includes: a first current mirror; a first bias current generator for providing a first bias current, and the first bias current generator includes: a first current source for providing the first current; and a capacitive device for conducting a reference current; a second current mirror for generating a second mirror current; a second bias current generator for generating a second current; a third current source for providing a third current, wherein the second mirror current is equal to the third current; a feedback circuit; and a fourth current source for providing a fourth current, wherein the output current is outputted at an output node of the first current mirror.