Patents by Inventor Yi-Wen Wu
Yi-Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250079428Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.Type: ApplicationFiled: November 15, 2024Publication date: March 6, 2025Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
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Patent number: 12237262Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.Type: GrantFiled: November 6, 2023Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng
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Patent number: 12176337Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.Type: GrantFiled: July 21, 2022Date of Patent: December 24, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
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Publication number: 20240379605Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Ting-Li Yang, Po-Hao Tsai, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu
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Publication number: 20240379536Abstract: Provided is a package structure including a die; an electrically connecting structure having a die attach region and a peripheral region surrounding the die attach region, wherein the die is disposed on the electrically connecting structure within the die attach region; an insulating protrusion disposed in the peripheral region and extending in a thickness direction of the die; a conductive structure disposed on the electrically connecting structure and encapsulating the insulating protrusion, wherein the conductive structure is electrically coupled to the electrically connecting structure and the die; and a dielectric structure disposed on the electrically connecting structure and encapsulating the die and the conductive structure.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20240363533Abstract: A package structure is provided. The package structure includes a first interconnect structure, a die structure over the first interconnect structure, and a dam structure on the die structure. The package structure also includes a second interconnect structure over the die structure and the dam structure. The package structure further includes a ring structure over the first interconnect structure and surrounding the die structure and the dam structure. In addition, the package structure includes a plurality of connectors electrically connected to the first interconnect structure and the second interconnect structure. A top surface of the ring structure is higher than a top surface of the first interconnect structure and lower than a top surface of each of the plurality of connectors.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao TSAI, Techi WONG, Meng-Liang LIN, Yi-Wen WU, Po-Yao CHUANG, Shin-Puu JENG
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Publication number: 20240332211Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.Type: ApplicationFiled: June 11, 2024Publication date: October 3, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang
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Patent number: 12094819Abstract: A method for forming a package structure is provided. The method includes forming a first interconnect structure over a carrier substrate and disposing a first die structure over the first interconnect structure. The method includes forming a dam structure over the first die structure. The method also includes forming a protection layer over a second interconnect structure. The method further includes bonding the second interconnect structure over the dam structure. In addition, the method includes forming a package layer between the first interconnect structure and the second interconnect structure. The method also includes removing the protection layer.Type: GrantFiled: August 18, 2021Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hao Tsai, Techi Wong, Meng-Liang Lin, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng
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Patent number: 12051654Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.Type: GrantFiled: July 27, 2023Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang
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Publication number: 20240178116Abstract: A semiconductor package includes a redistribution structure and an encapsulated die electrically connected to the redistribution structure. The redistribution structure includes a first conductive pad, first and second conductive vias, and a first dielectric layer. The first conductive pad includes opposing first and second sides, the first conductive via lands on the first side of the first conductive pad and is tapered in a direction from the first side toward the second side. The second conductive via lands on the second side of the first conductive pad and is tapered in a direction from the second side toward the first side. The first dielectric layer laterally covers the first conductive pad and the first conductive via, and the first dielectric layer includes opposing first and second surfaces. The encapsulated die is disposed below the first side of the first conductive via.Type: ApplicationFiled: January 10, 2024Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
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Publication number: 20240071909Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen WU, Techi WONG, Po-Hao TSAI, Po-Yao CHUANG, Shih-Ting HUNG, Shin-Puu JENG
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Patent number: 11901279Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.Type: GrantFiled: March 14, 2023Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
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Patent number: 11901277Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.Type: GrantFiled: July 3, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
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Patent number: 11855014Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.Type: GrantFiled: December 14, 2020Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Yi-Wen Wu, Tzung-Hui Lee
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Patent number: 11855028Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.Type: GrantFiled: May 21, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURINGInventors: Ting-Li Yang, Po-Hao Tsai, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu
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Patent number: 11848265Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.Type: GrantFiled: August 12, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng
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Publication number: 20230387028Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
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Publication number: 20230378089Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung, Po-Yao chuang
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Publication number: 20230378055Abstract: A semiconductor package is provided. The semiconductor package includes a redistribution structure, a semiconductor die, and an interposer structure. The interposer structure includes an insulating base having a first surface facing the semiconductor die and a second surface opposite to the first surface and conductive features formed over the insulating base. The conductive features include first portions on the first surface of the insulating base and vertically overlapping the semiconductor die, second portions on the first surface of the insulating base and located outside a projection area of the semiconductor die in a top view, third portions on the second surface of the insulating base and vertically overlapping the semiconductor die, and fourth portions on the second surface of the insulating base and located outside the projection area of the semiconductor die in the top view. The interposer structure includes capping layers and dielectric features.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen WU, Techi WONG, Po-Hao TSAI, Po-Yao CHUANG, Shih-Ting HUNG, Shin-Puu JENG
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Patent number: 11824007Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.Type: GrantFiled: March 9, 2022Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong