Patents by Inventor Yi-Wen Wu
Yi-Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11600573Abstract: A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.Type: GrantFiled: June 26, 2019Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Tsai, Techi Wong, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng
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Publication number: 20230061716Abstract: Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.Type: ApplicationFiled: March 29, 2022Publication date: March 2, 2023Inventors: Yen-Kun Lai, Yi-Wen Wu, Kuo-Chin Chang, Po-Hao Tsai, Mirng-Ji Lii
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Patent number: 11594484Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.Type: GrantFiled: June 29, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
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Publication number: 20220359489Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
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Publication number: 20220336337Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.Type: ApplicationFiled: July 3, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
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Publication number: 20220310468Abstract: A package structure is provided. The package structure includes a redistribution structure, and the redistribution structure has multiple insulating layers and multiple conductive features. The package structure also includes a semiconductor die and a device element over opposite surfaces of the redistribution structure. The package structure further includes a first protective layer at least partially surrounding the semiconductor die. In addition, the package structure includes a second protective layer at least partially surrounding the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Meng-Liang LIN, Po-Hao TSAI, Po-Yao CHUANG, Yi-Wen WU, Techi WONG, Shin-Puu JENG
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Patent number: 11430776Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.Type: GrantFiled: June 15, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
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Patent number: 11410953Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.Type: GrantFiled: August 3, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
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Publication number: 20220238456Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang
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Publication number: 20220230978Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.Type: ApplicationFiled: May 21, 2021Publication date: July 21, 2022Inventors: Ting-Li Yang, Po-Hao Tsai, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu
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Publication number: 20220199541Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
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Patent number: 11362010Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die over a first surface of a redistribution structure. The method also includes forming a first protective layer to surround a portion of the semiconductor die. The method further includes disposing a device element over a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method includes forming a second protective layer to surround a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.Type: GrantFiled: October 16, 2019Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Liang Lin, Po-Hao Tsai, Po-Yao Chuang, Yi-Wen Wu, Techi Wong, Shin-Puu Jeng
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Patent number: 11322447Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.Type: GrantFiled: March 6, 2020Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
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Patent number: 11302650Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.Type: GrantFiled: July 6, 2020Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang
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Patent number: 11257714Abstract: An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.Type: GrantFiled: July 21, 2015Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
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Patent number: 11239233Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.Type: GrantFiled: September 5, 2019Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20210391317Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
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Publication number: 20210384125Abstract: A method for forming a package structure is provided. The method includes forming a first interconnect structure over a carrier substrate and disposing a first die structure over the first interconnect structure. The method includes forming a dam structure over the first die structure. The method also includes forming a protection layer over a second interconnect structure. The method further includes bonding the second interconnect structure over the dam structure. In addition, the method includes forming a package layer between the first interconnect structure and the second interconnect structure. The method also includes removing the protection layer.Type: ApplicationFiled: August 18, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao TSAI, Techi WONG, Meng-Liang LIN, Yi-Wen WU, Po-Yao CHUANG, Shin-Puu JENG
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Publication number: 20210375755Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng
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Patent number: 11133265Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.Type: GrantFiled: December 16, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Yi-Wen Wu