Patents by Inventor Yi-Wen Wu

Yi-Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9691738
    Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
  • Patent number: 9685372
    Abstract: A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Hui-Jung Tsai, Yi-Wen Wu, Chung-Shi Liu
  • Publication number: 20170141060
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Hsien-Wei Chen, Yi-Wen Wu
  • Patent number: 9653418
    Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Che Ho, Yi-Wen Wu
  • Publication number: 20170110401
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kio-Chio Liu
  • Patent number: 9607921
    Abstract: A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Yi-Wen Wu, Chih-Wei Lin, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20170084563
    Abstract: A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Chien Ling HWANG, Yi-Wen WU, Chung-Shi LIU
  • Patent number: 9601355
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 9559070
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yi-Wen Wu
  • Patent number: 9548283
    Abstract: A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Hung-Jui Kuo, Yi-Wen Wu
  • Patent number: 9524945
    Abstract: An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: December 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Patent number: 9418956
    Abstract: A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Lin, Ming-Che Ho, Yu-Feng Chen, Yi-Wen Wu, Hsien-Liang Meng, Han-Ping Pu
  • Publication number: 20160218075
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Application
    Filed: April 4, 2016
    Publication date: July 28, 2016
    Inventors: Hsien-Wei Chen, Yi-Wen Wu
  • Patent number: 9385076
    Abstract: A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Yi-Wen Wu, Wen-Hsiung Lu
  • Patent number: 9368462
    Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Ming-Che Ho, Wen-Hsiung Lu, Chia-Wei Tu, Chung-Shi Liu
  • Publication number: 20160155650
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 2, 2016
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 9305856
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yi-Wen Wu
  • Patent number: 9287171
    Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen Wu, Cheng-Chung Lin, Chien Ling Hwang, Chung-Shi Liu
  • Patent number: 9263302
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Publication number: 20150364449
    Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu