Abstract: An antenna power adjustment method is provided and applied to an electronic device. The antenna power adjustment method includes: performing position detection by a first acceleration detector and a second acceleration detector, where the first acceleration detector and the second acceleration detector are respectively disposed on a first plate and a second plate of the electronic device, and the first plate and the second plate are connected to each other by using a pivot of the electronic device for relative rotation; calculating an angle between the first plate and the second plate according to results of the position detection of the first acceleration detector and the second acceleration detector; and adjusting a power of an antenna of the electronic device according to the angle.

Abstract: Techniques related to disparity search range compression are discussed. Such techniques may include determining a combination of disparity search values that do not coexist in any search range of multiple search ranges each associated with pixels of an initial disparity map, compressing the combination of disparity values to a single disparity label, and performing a disparity estimation based on a disparity search label set including the single disparity label.

Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Abstract: A circuit board for testing and a method of operating the same are provided. A relay is installed on a body of a circuit board having a probe. At least one external conductive line is arranged between the probe and the relay. During high-frequency signal testing, a transmission route is to transmit high-frequency signals to a test machine by means of the external conductive line, but is not to transmit high-frequency signals to a test machine by means of the relay. Accordingly, the limitation of the bandwidth condition of the relay can be avoided.

Abstract: A light-emitting diode chip includes a light-emitting epitaxial laminated layer including a first-type semiconductor layer, a second-type semiconductor layer, and an active layer therebetween, wherein the light-emitting epitaxial laminated layer has a first surface and an opposing second surface, and wherein the second surface is a light-emitting surface; a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer and having first geometric pattern arrays; a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer and having second geometric pattern arrays; and a transparent current spreading layer over a surface of the second electrical connection layer; wherein, when external power is connected, a horizontal resistance of a current passing through the transparent current spreading layer is less than a current passing through the second electrical connection layer.

Abstract: An electronic device package includes a carrying board, an electronic device, a first insulating layer, and a barrier layer. The carrying board includes a central area, an inner edge area, and an outer edge area. The inner edge area is located between the central area and the outer edge area. The electronic device is located in the central area. The first insulating layer is located on the carrying board and overlapped with the electronic device and extends from the central area to the inner edge area. The barrier layer is located on the carrying board. Here, the barrier layer includes a sidewall contact portion and an extending portion. The sidewall contact portion surrounds a side surface of the first insulating layer, and the extending portion extends from the sidewall contact portion to the outer edge area in a direction away from the first insulating layer.

Abstract: A polymerizable composition is provided, including an infrared absorber, a polymerization initiator, a polymerizable compound, and a polymer binder, wherein the polymer binder is a particulate random copolymer, and the polymer binder has structural units derived from a polymerizable polyalkylene oxide-based monomer and a polymerizable nitrogen-free non-polyalkylene oxide-based monomer. The polymerizable composition may be used in the production of imageable elements or printing plates.

Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.

Abstract: The present invention provides a DC circuit breaker combining magnetic induction transfer and resistance current limiting, the circuit breaker comprising: a main current circuit, a current-limiting branch, a breaking branch, and an energy dissipation branch; the current-limiting branch and the breaking circuit each comprises a magnetic induction transfer module; an inductor in the magnetic induction transfer module of the current-limiting branch and a branch inductor in the current-limiting branch are coupled to form a mutual inductor; an inductor in the magnetic induction transfer module of the breaking branch and a second inductor in the transfer current loop are coupled to form a mutual inductor. The present invention can limit the current rising speed and amplitude and completely turned off the short-circuit current, thereby reducing the size and manufacturing cost of the circuit breaker.

Abstract: The present invention relates to a power circuit of displaying device, which comprises a timing controller, a control circuit, and a charge pump (single or multiple stages). The timing controller outputs a timing control signal to the control circuit. The control circuit outputs a clock signal or a capacitance adjusting signal according to the timing control signal. The charge pump receives the input voltage and outputs an output voltage according to the clock signal or the capacitance adjusting signal. The output voltage is provided to the scan driver for generating a plurality of scan driving signals. Accordingly, by increasing the rise rate of the output voltage of the charge pump in the voltage conversion time and reducing the rise rate of the output voltage close to the voltage holding time, the present invention can achieve the effect of reducing the power consumption.

Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

Abstract: The present disclosure provides an arc-free DC circuit breaker that combines magnetic induction transfer and resistive current limiting. The circuit breaker comprises a main current circuit and a transfer current circuit. The transfer current circuit has a bridge structure; with a group of unidirectional components having a breaking function, bidirectional current breaking is implemented, such that compared with the prior art, usage of the turn-off devices may be reduced to half. By controlling action sequences of the trigger gap, high-speed switch, and power semiconductor, fast switching arc-free opening of the main current circuit is implemented; meanwhile, the breaking capability of the circuit breaker is significantly improved. By virtue of the current limiting module circuit inside the transfer current circuit, the present disclosure quickly limits short-circuit fault current, and then reduces the number of parallel groups of full-controlled devices of the breaking module circuit.

Abstract: A pixel structure includes data lines disposed along a first direction, scan lines disposed along a second direction and pixel units periodically disposed along the first and the second directions. In a first pixel unit, a first switch element is coupled to a first scan line and a first data line, the second switch element is coupled to the first scan line, and a third switch element is coupled to the first scan line. In a second pixel unit, a fourth switch element is coupled to a second scan line, the first data line and the second switch element, and a fifth switch element is electrically coupled to the second scan line and the third switch element. In a third pixel unit, a sixth switch element is coupled to a third scan line, the first data line and the fifth switch element.

Abstract: The present disclosure provides a hybrid circuit breaker having a bridge induction transfer structure, characterized in that the circuit breaker comprises a main current circuit, an over-voltage limiting circuit, and a transfer current circuit; and the main current circuit, the over-voltage limiting circuit, and the transfer current circuit are connected in parallel. The induction transfer circuit in the transfer current circuit comprises an induction transfer inductor, an induction transfer capacitor, and an induction transfer branch power semiconductor device which are connected in series; the transfer current circuit further comprises a bridge circuit comprised of a main loop capacitor; the main loop inductor and the induction transfer inductor are coupled to form a transformer. The present invention can implement fast breaking of the current, and effectively reduce the volume and manufacturing cost of the circuit breaker. With the induction transfer circuit, fast current transfer is implemented.

Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

Abstract: A system, method and program product for implementing a simplified touch screen interface for collecting character data. a device is disclosed having a touch screen interface, wherein the touch screen interface includes: a primary view that displays rotating character sets, wherein each one of the character sets sequentially rotates into an active position, and wherein a character set in the active position is selectable in response to a first touch to a uniform input region; a secondary view that displays rotating characters, wherein each one of the rotating characters sequentially rotates into the active position, and wherein a character in the active position is selectable in response to a second touch to the uniform input region; and wherein the rotating characters displayed in the secondary view are determined based on the character set selected in the primary view.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over an underlying structure disposed on a substrate. A planarization resistance layer is formed over the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the planarization resistance layer. A planarization operation is performed on the second dielectric layer, the planarization resistance layer and the first dielectric layer. The planarization resistance film is made of a material different from the first dielectric layer.

Abstract: A light-emitting diode includes a light-emitting epitaxial laminated layer with an upper surface; an ohmic contact layer over the light-emitting epitaxial laminated layer; an expanding electrode over the ohmic contact layer; a transparent insulating layer that covers the expanding electrode and the exposed ohmic contact layer, having a hole through the transparent insulating layer in a position corresponding to the expanding electrode; and a welding wire electrode over the transparent insulating layer and coupled to the expanding electrode via the hole.

Abstract: An antenna unit includes a first metal portion, a second metal portion connected to one side of the first metal portion, a third metal portion connected to another side of the first metal portion and opposite to the second metal portion, a feed point disposed at the second metal portion, a first ground terminal, and a second ground terminal. The feed point, the first ground terminal and the second ground terminal are disposed in a straight line. The shape of the first metal portion is mirror-image symmetrical relative to the feed point, the first ground terminal and the second ground terminal.

Abstract: In one example in accordance with the present disclosure, a system is provided. The system includes a first subsystem and a second subsystem, connectable to each other via a passive cable, and each connected to a high-level management tool. Each subsystem includes a signal driver/receiver capable of sending and receiving data and signals over the passive cable and a connection discovery engine to access low-level power up/down controls of the signal driver/receiver. The connection discovery engine is to, via physical layer communication, send a local unique identifier (ID) of the particular signal driver/receiver over the passive cable. The connection discovery engine is further to, via physical layer communication, receive, over the passive cable, a remote unique ID of the signal driver/receiver in the other connected subsystem. The connection discovery engine is further to send the local unique ID and the remote unique ID to the high-level management tool.