Patents by Inventor Yi Wu

Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190140320
    Abstract: An electrolyte composition including a heterocyclic compound, an electrolyte salt and a solvent is provided. The heterocyclic compound includes, in the heterocyclic ring: (a) at least two nitrogen atoms each of which is bonded to a —Si(R1)3 group; and (b) at least one carbonyl group (C?O) or thiocarbonyl group (C?S) wherein R1 is a C1-3 alkyl group or an aryl group. The electrolyte composition of the present disclosure is suitable for an electrochemical device. Electrochemical devices, in particular batteries, using the electrolyte composition of else present disclosure are capable of efficiently inhibiting the moisture and acidity therein, thereby stabilizing the electrolyte salt therein, and preventing the electrolyte salt from being further decomposed and from producing hydrogen fluoride.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 9, 2019
    Applicant: ETERNAL MATERIALS CO., LTD.
    Inventors: WEI-CHIH CHEN, TU-YI WU, CHIH HSIEN WANG, YI-FANG JUNG
  • Publication number: 20190135932
    Abstract: The present disclosure provides isolated binding molecules that bind to the human OX40R, nucleic acid molecules encoding an amino acid sequence of the binding molecules, vectors comprising the nucleic acid molecules, host cells containing the vectors, methods of making the binding molecules, pharmaceutical compositions containing the binding molecules, and methods of using the binding molecules or compositions.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 9, 2019
    Applicants: Pfizer Inc., Bristol-Myers Squibb Company
    Inventors: Jing MIN, Yanli WU, Rory F. FINN, Barrett R. THIELE, Wei LIAO, Ronald P. GLADUE, Arvind RAJPAL, Timothy J. PARADIS, Peter BRAMS, Brigitte DEVAUX, Yi WU, Kristopher TOY, Heidi N. LEBLANC, Haichun HUANG
  • Publication number: 20190140208
    Abstract: A method of manufacturing a flip-chip light emitting diode includes: providing a transparent substrate and a temporary substrate, and bonding the transparent substrate with the temporary substrate; grinding and thinning the transparent substrate; providing a light-emitting epitaxial laminated layer having a first surface and a second surface opposite to each other, and including a first semiconductor layer, an active layer and a second semiconductor layer; forming a transparent bonding medium layer over the first surface of the light-emitting epitaxial laminated layer, and bonding the transparent bonding medium layer with the transparent substrate; defining a first electrode region and a second electrode region over the second surface of the light-emitting epitaxial laminated layer, and manufacturing a first electrode and a second electrode; and removing the temporary substrate
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Shu-Fan YANG, Chun-Yi WU, Chaoyu WU
  • Patent number: 10283495
    Abstract: A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Chun-Yi Lee, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee, Tung-Heng Hsieh, Tsung-Chieh Tsai
  • Publication number: 20190129192
    Abstract: The disclosure is related to a method for rendering a three-dimensional image, an imaging method and a system. The system receives three-dimensional image information regarding. A reference image with respect to the three-dimensional image can be created based on the information. According to the physical information relating to multiple optical elements of a display device, an element image corresponding to each optical element is calculated. The multiple elements images corresponding to the multiple optical elements render an integral image. The integral image is used to render the three-dimensional image through the multiple optical elements. In one embodiment, the optical element is a lens set. The integral image is inputted to a display driving unit of the display device so as to render the element image for every lens set. The display device then displays the integral image so as to from the three-dimensional image through a lens array.
    Type: Application
    Filed: January 10, 2018
    Publication date: May 2, 2019
    Inventors: CHUN-HSIANG YANG, YI-PAI HUANG, KAI-CHIEH CHANG, CHIH-HUNG TING, JUI-YI WU
  • Publication number: 20190131134
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Hong-Ying LIN, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sean Lo, C.W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Patent number: 10274488
    Abstract: Aluminum coated glass slides provide a novel glycan array platform. Specifically, aluminum coated glass slides increase sensitivity of fluorescent based assay methods. Additionally, aluminum coated glass slides allows for mass spectroscopic analysis of carbohydrates and provide a platform for examining activity of cellulases. The unique properties of ACG slides include: 1) the metal oxide layer on the surface can be activated for grafting organic compounds such as modified oligosaccharides; 2) the surface remains electrically conductive, and the grafted oligosaccharides can be simultaneously characterized by mass spectrometry and carbohydrate-binding assay; and 3) the slides are more sensitive than transparent glass slides in binding analysis.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 30, 2019
    Assignee: ACADEMIA SINICA
    Inventors: Chi-Huey Wong, Chung-Yi Wu, Susan Y. Tseng
  • Patent number: 10275559
    Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
  • Publication number: 20190123103
    Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 25, 2019
    Inventor: JAU-YI WU
  • Publication number: 20190119713
    Abstract: The present disclosure relates to glycoproteins, particularly monoclonal antibodies, comprising a glycoengineered Fc region, wherein said Fc region comprises an optimized N-glycan having the structure of Sia2(?2-6)Gal2GlcNAc2Man3GlcNAc2. The glycoengineered Fc region binds Fc?RIIA or Fc?RIIIA with a greater affinity, relative to comparable monoclonal antibodies comprising the wild-type Fc region. The monoclonal antibodies of the invention are particularly useful in preventing, treating, or ameliorating one or more symptoms associated with a disease, disorder, or infection where an enhanced efficacy of effector cell function (e.g., ADCC) mediated by Fc?R is desired, e.g., cancer, autoimmune, infectious disease, and in enhancing the therapeutic efficacy of therapeutic antibodies the effect of which is mediated by ADCC.
    Type: Application
    Filed: June 26, 2018
    Publication date: April 25, 2019
    Applicant: Academia Sinica
    Inventors: Chi-Huey WONG, Chung-Yi WU, Che MA
  • Publication number: 20190122976
    Abstract: A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20190123423
    Abstract: An antenna structure including a metal outer cover and an antenna assembly is provided. The metal outer cover has a bent slit. The antenna assembly is stacked on the metal outer cover and covers a portion of the bent slit. The antenna assembly includes a substrate and an antenna pattern disposed on the substrate. The antenna pattern includes a feed end, a first ground end and a second ground end. In the antenna pattern, a first loop and a second loop are formed from the feed end to the first ground end in two respective paths. A third loop is formed from the feed end to the second ground end. The first loop and the third loop resonate with the bent slit to generate a low frequency band and a portion of a high frequency band. The second loop and the third loop resonate with the bent slit to generate another portion of the high frequency band. An electronic device having the antenna structure is further provided.
    Type: Application
    Filed: August 21, 2018
    Publication date: April 25, 2019
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Ching-Hsiang Ko, Cheng-Hsiung Wu, Shih-Keng Huang
  • Patent number: 10269785
    Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 10270173
    Abstract: A patch antenna includes a grounding portion and a radiating portion. The radiating portion includes a first feeding point, a first grounding point, a second feeding point, and a second grounding point. The first feeding point is electrically connected to a first signal source. The first grounding point is electrically connected to the grounding portion. The second feeding point is electrically connected to a second signal source. The second grounding point electrically connected to the grounding portion. The line formed by connecting the first feeding point and the first grounding point is substantially perpendicular to the line formed by connecting the second feeding point and the second grounding point.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: April 23, 2019
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Ya-Jyun Li, Chao-Hsu Wu, Shih-Keng Huang, Hung-Ming Yu
  • Patent number: 10270158
    Abstract: A wearable electronic device is disclosed. Wearable electronic device includes a metal casing, a dielectric support part, a frame-shaped metal part, a dielectric sidewall and a first antenna wired circuit. The metal casing is electrically connected to the system ground. The dielectric support part is disposed on the metal casing. The frame-shaped metal part is disposed on the dielectric support part. One side of the frame-shaped metal part is electrically connected to the metal casing and another side of the frame-shaped metal part has a slot. The dielectric sidewall is surrounding within the metal casing. The first antenna wired circuit is disposed on the inner surface of the dielectric sidewall and insulated from the metal casing. The first antenna wired circuit is near the slot. The first antenna wired circuit and the frame-shaped metal part resonate a first resonant frequency band.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: April 23, 2019
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Shih-Keng Huang, Ya-Jyun Li
  • Publication number: 20190113766
    Abstract: A display method of a light field image adapted to a light field display apparatus is provided. The display method includes the following: providing an image having a plurality of depth values, wherein the depth values represent degrees of distance of the image; respectively obtaining a plurality of pixels in the image corresponding to the depth values respectively falling within a plurality of different extended depth value ranges based on the extended depth value ranges to from a plurality of layered images, wherein the extended depth value ranges are different from each other and are partially overlapped in sequence; forming the light field image based on the plurality of layered images; and providing a signal corresponding to the light field image to a display of the light field display apparatus. In addition, the light field display apparatus is also provided.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 18, 2019
    Applicant: Coretronic Corporation
    Inventors: Han-Hsuan Lin, Jui-Yi Wu
  • Patent number: 10263064
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor device includes an inductor structure, and the inductor structure is on a substrate and includes a first metal layer, a magnetic stack, a polymer layer and a second metal layer. The first metal layer is over the substrate. The magnetic stack is over the first metal layer and has a substantially zigzag shaped sidewall. The polymer layer is over the first metal layer and encapsulates the magnetic stack. The second metal layer is over the polymer layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chien-Chih Chou, Chen-Shien Chen, Hon-Lin Huang, Chi-Cheng Chen, Kuang-Yi Wu
  • Publication number: 20190100573
    Abstract: Modified Fc regions of antibodies and antibody fragments, both human and humanized, and having enhanced stability and efficacy, are provided. Fc regions with core fucose residues removed, and attached to oligosaccharides comprising terminal sialyl residues, are provided. Antibodies comprising homogeneous glycosylation of Fc regions with specific oligosaccharides are provided. Fc regions conjugated with homogeneous glycoforms of monosaccharides and trisaccharides, are provided. Methods of preparing human antibodies with modified Fc using glycan engineering, are provided.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 4, 2019
    Inventors: Chi-Huey WONG, Chung-Yi WU
  • Publication number: 20190103236
    Abstract: A key structure includes a movable support element, a keycap, and a fitting portion. The keycap includes a top surface, a bottom surface, and a rim, the bottom surface is jointed with the movable support element, and a periphery of the top surface extends downward to form the rim. The fitting portion is located on the rim, and operated by an operation body to separate the keycap from the movable support element.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Inventors: Meng-Chu Huang, Tong-Shen Hsiung, Jau-Yi Wu, Li-Wei Yu, Chen-Hou Lo
  • Publication number: 20190103353
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Application
    Filed: August 1, 2018
    Publication date: April 4, 2019
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou