Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.

Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.

Abstract: An apparatus for estimating a carrier frequency offset (CFO) is provided. A differential correlation calculation is performed on a received signal and a reference signal to generate multiple calculation results. One among M number of peak values with largest amplitudes determined from the calculation results is selected as a candidate peak value and outputted each time. A data capturing circuit captures from the received signal a data segment corresponding to the candidate peak value as a candidate data segment. A fast Fourier transform (FFT) circuit performs FFT on a product of the candidate data segment and a conjugate signal of reference data to obtain a candidate transform result. A selecting circuit determines whether to select the candidate transform result as a target transform result. The CFO calculating circuit determines an estimated CFO according to a frequency corresponding to the largest amplitude in the target transform result.

Abstract: A phase recovery device includes a phase recovery module and a residual phase recovery module. The phase recovery module performs a first-stage phase recovery on a received signal to generate a first phase recovered signal. The residual phase recovery module performs a second-stage phase recovery on the first phase-recovered signal to generate a second phase recovered signal.

Abstract: A packet output device includes: a first extracting unit, extracting a plurality of first packets and a plurality of first null packet values corresponding to a first channel; a first buffer, storing the first packets and the first null packet values; a second extracting unit, extracting a plurality of second packets and a plurality of second null packet values corresponding to a second channel; a second buffer, storing the second packets and the second null packet values; and a packet outputting unit, selecting, according to the first null packet values and the second null packet values, one of the first packets and the second packets as an output packet.

Abstract: A method for detecting a notch band is applied to a multicarrier communication system that operates in a wideband. The method includes: receiving a received signal, and generating a plurality of frequency-domain signals according to the received signal; performing a magnitude operation on the frequency-domain signals to obtain a plurality of magnitude values; determining a plurality of ratios of a first magnitude set among the magnitude values to a second magnitude set among the magnitude value to determine whether the received signal contains a notch band.

Abstract: A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

Abstract: A decoding apparatus includes an input power estimating circuit, an error correction decoder and a controller. The input power estimating circuit generates multiple estimated input powers for multiple sets of data included in a packet that needs to be corrected, and calculates respective power differences between the multiple estimated input powers and a reference power. The controller determines one or multiple candidate error positions according to one of the multiple power differences that is higher than a predetermined threshold. The error correction decoder performs a decoding process on the packet according to the one or multiple candidate error positions.

Abstract: A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

Abstract: A receiving circuit capable of estimating frequency offset includes a front circuit and a calculation circuit. The front circuit receives a remote signal to generate a received signal. The calculation circuit includes: an exponentiation module, calculating an exponent of a power to generate a high-order signal; a frequency-domain transform module, performing frequency-domain transform on the high-order signal to generate a spectrum; a peak searching module, searching for a peak of the amplitude of the spectrum to generate a peak coordinate value reflecting a frequency where the peak occurs; an offset estimating module, adding the peak coordinate value with a compensation value to generate a sum, dividing the sum by a first divisor to generate a remainder, subtracting the compensation value from the remainder to generate a difference, and dividing the difference by a second divisor to generate an offset estimation value reflecting the frequency offset.

Abstract: A signal processing device of a television receiving end is provided. The television receiving end includes a tuner, which receives a television signal including a preamble signal. The signal processing device includes: an analog-to-digital converter, converting the television signal from an analog format to a digital format; an FFT circuit, transforming the television signal in the digital format to a frequency domain; a preamble data detecting circuit, detecting the preamble signal in the frequency-domain television signal to generate a preamble data detection result; a frequency notch detecting circuit, detecting a frequency notch of the preamble signal in the frequency-domain television signal according to the preamble data detection result to generate a frequency notch detection result; and a decoder, decoding the frequency-domain television signal to generate decoded data. The frequency notch detection result is for the tuner to accordingly determine whether to change the receiving frequency band.

Abstract: A decoding apparatus includes a differential decoder, an error correction decoder and a controller. The differential decoder performs differential decoding according to a differential encoding dependency to generate a differential decoding result. The error correction decoder performs a decoding process on multiple packets that need to be corrected according to the differential decoding result to accordingly generate respective error correction records, wherein the packets are generated according to the differential decoding results, and the packets include a first packet and a second packet. When the error correction record of the first packet indicates that the decoding process of the first packet is unsuccessful, the controller generates a set of error position information according to the error correction record of the second packet, and requests the error correction decoder to perform another decoding process on the first packet according to the error position information.

Abstract: A multimedia processing system for processing a plurality of transport streams of different digital video broadcasting standards includes: a configuration module, generating a control signal; a descrambler, receiving a single transport stream and the control signal to generate header information, data information and padding information; a data processing module, generating an input stream synchronization signal and transport stream packet processed information according to the output of the descrambler; a timing control module, receiving the padding information, the input transport stream synchronization signal and the control signal to generate a time-to-output signal and a packet interval signal; and an output module, receiving the time-to-output signal, the packet interval signal, the transport stream packet processed information and the control signal to generate output stream information.

Abstract: A time-domain equalizer for eliminating an echo signal from a received signal is provided. The received signal includes an original signal and the echo signal. The time-domain equalizer includes a time delay estimator, an amplitude amplifying ratio estimator and a phase shift estimator. The time delay estimator determines a delay amount maximizing a cost function to serve as an estimated delay amount of the echo signal relative to the original signal. The amplitude amplifying ratio estimator determines an estimated amplitude amplifying ratio of the echo signal relative to the original signal. The phase shift estimator determines an estimated phase shift of the echo signal relative to the original signal according to the estimated delay amount. The estimated delay amount, the estimated amplitude amplifying ratio and the estimated phase shift are used to set a filtering condition to be applied to the received signal.

Abstract: A decoding apparatus includes an input power estimating circuit, an error correction decoder and a controller. The input power estimating circuit generates multiple estimated input powers for multiple sets of data included in a packet that needs to be corrected, and calculates respective power differences between the multiple estimated input powers and a reference power. The controller determines one or multiple candidate error positions according to one of the multiple power differences that is higher than a predetermined threshold. The error correction decoder performs a decoding process on the packet according to the one or multiple candidate error positions.

Abstract: A method for detecting a notch band is applied to a multicarrier communication system that operates in a wideband. The method includes: receiving a received signal, and generating a plurality of frequency-domain signals according to the received signal; performing a magnitude operation on the frequency-domain signals to obtain a plurality of magnitude values; determining a plurality of ratios of a first magnitude set among the magnitude values to a second magnitude set among the magnitude value to determine whether the received signal contains a notch band.

Abstract: A decoding apparatus includes a differential decoder, an error correction decoder and a controller. The differential decoder performs differential decoding according to a differential encoding dependency to generate a differential decoding result. The error correction decoder performs a decoding process on multiple packets that need to be corrected according to the differential decoding result to accordingly generate respective error correction records, wherein the packets are generated according to the differential decoding results, and the packets include a first packet and a second packet. When the error correction record of the first packet indicates that the decoding process of the first packet is unsuccessful, the controller generates a set of error position information according to the error correction record of the second packet, and requests the error correction decoder to perform another decoding process on the first packet according to the error position information.