Patents by Inventor Yidnekachew S. Mekonnen
Yidnekachew S. Mekonnen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352412Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.Type: ApplicationFiled: July 12, 2023Publication date: November 2, 2023Inventors: Yidnekachew S. MEKONNEN, Kemel AYGUN, Ravindranath V. MAHAJAN, Christopher S. BALDWIN, Rajasekaran SWAMINATHAN
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Patent number: 11791528Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: GrantFiled: April 6, 2022Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
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Patent number: 11742293Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.Type: GrantFiled: March 22, 2017Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Yidnekachew S. Mekonnen, Kemel Aygun, Ravindranath V. Mahajan, Christopher S. Baldwin, Rajasekaran Swaminathan
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Patent number: 11545416Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.Type: GrantFiled: September 30, 2017Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Jianyong Xie, Yidnekachew S. Mekonnen, Zhiguo Qian, Kemal Aygun
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Patent number: 11437366Abstract: Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.Type: GrantFiled: September 29, 2017Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Zhichao Zhang, Kemal Aygun, Yidnekachew S. Mekonnen
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Publication number: 20220231394Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Inventors: Adel A. ELSHERBINI, Mathew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
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Patent number: 11329358Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: GrantFiled: April 6, 2020Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
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Patent number: 11322445Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.Type: GrantFiled: September 12, 2016Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Yidnekachew S. Mekonnen, Dae-Woo Kim, Kemal Aygun, Sujit Sharan
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Publication number: 20210296240Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.Type: ApplicationFiled: September 12, 2016Publication date: September 23, 2021Inventors: Yidnekachew S. Mekonnen, Dae-Woo Kim, Kemal Aygun, Sujit Sharan
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Patent number: 10992342Abstract: Technology for simplified multimode signaling includes determining first and second self ?-terms, cross coupling ?-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self ?-terms, the cross coupling ?-terms and the delay skew term.Type: GrantFiled: March 1, 2017Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Yidnekachew S. Mekonnen, Kemal Aygun, Henning Braunisch
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Patent number: 10971416Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.Type: GrantFiled: July 30, 2019Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
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Publication number: 20210074333Abstract: Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.Type: ApplicationFiled: October 30, 2020Publication date: March 11, 2021Inventors: Chong J. ZHAO, James A. McCALL, Robert J. FRIAR, Yidnekachew S. MEKONNEN, San K. CHHAY
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Patent number: 10784204Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.Type: GrantFiled: July 2, 2016Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
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Publication number: 20200279793Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.Type: ApplicationFiled: September 30, 2017Publication date: September 3, 2020Applicant: Intel CorporationInventors: Jianyong XIE, Yidnekachew S. Mekonnen, Zhiguo Qian, Kemal Aygun
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Publication number: 20200235449Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: ApplicationFiled: April 6, 2020Publication date: July 23, 2020Inventors: Adel A. ELSHERBINI, Mathew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
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Patent number: 10651525Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: GrantFiled: June 4, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
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Publication number: 20200066641Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.Type: ApplicationFiled: July 2, 2016Publication date: February 27, 2020Inventors: Kemal AYGUN, Richard J. DISCHLER, Jeff C. MORRISS, Zhiguo QIAN, Wilfred GOMES, Yu Amos ZHANG, Ram S. VISWANATH, Rajasekaran SWAMINATHAN, Sriram SRINIVASAN, Yidnekachew S. MEKONNEN, Sanka GANESAN, Eduard ROYTMAN, Mathew J. MANUSHAROW
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Publication number: 20200021330Abstract: Technology for simplified multimode signaling includes determining first and second self ?-terms, cross coupling ?-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self ?-terms, the cross coupling ?-terms and the delay skew term.Type: ApplicationFiled: March 1, 2017Publication date: January 16, 2020Applicant: Intel CorporationInventors: Yidnekachew S. Mekonnen, Kemal Aygun, Henning Braunisch
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Publication number: 20190363049Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.Type: ApplicationFiled: March 22, 2017Publication date: November 28, 2019Inventors: Yidnekachew S. MEKONNEN, Kemel AYGUN, Ravindranath V. MAHAJAN, Christopher S. BALDWIN, Rajasekaran SWAMINATHAN
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Publication number: 20190355636Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao