Patents by Inventor Yidnekachew S. Mekonnen

Yidnekachew S. Mekonnen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410939
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Patent number: 10396036
    Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Zhiguo Qian, Kemal Aygun, Yidnekachew S. Mekonnen, Gregorio R. Murtagian, Sanka Ganesan, Eduard Roytman, Jeff C. Morriss
  • Publication number: 20190252321
    Abstract: Disclosed is a signaling system. The signaling system may comprise a transmitter, a receiver, and a package interconnect. The transmitter may be configured to transmit M signals. The receiver may be configured to receive the M signals. The package interconnect may include a bundle of N wires electrically connecting the transmitter and the receiver. During operation, the N wires may be electromagnetically coupled with each other and the M signals may travel between the transmitter and the receiver on the bundle of N wires.
    Type: Application
    Filed: September 28, 2016
    Publication date: August 15, 2019
    Inventors: Henning Braunisch, Kemal Aygun, Yidnekachew S. Mekonnen
  • Patent number: 10186465
    Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel A. Elsherbini, Henning Braunisch, Yidnekachew S. Mekonnen, Krishna Bharath, Mathew J. Manusharow, Aleksandar Aleksov, Nathan Fritz
  • Publication number: 20180331003
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: December 16, 2015
    Publication date: November 15, 2018
    Inventors: Krishna BHARATH, Mathew J. MANUSHAROW, Adel A. ELSHERBINI, Mihir K. ROY, Aleksandar ALEKSOV, Yidnekachew S. MEKONNEN, Javier SOTO GONZALEZ, Feras EID, Suddhasattwa NAD, Meizi JIAO
  • Publication number: 20180331043
    Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Inventors: Yu Amos ZHANG, Zhiguo QIAN, Kemal AYGUN, Yidnekachew S. MEKONNEN, Gregorio R. MURTAGIAN, Sanka GANESAN, Eduard ROYTMAN, Jeff C. MORRISS
  • Publication number: 20180288868
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Adel A. ELSHERBINI, Matthew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
  • Patent number: 9992859
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Publication number: 20180005989
    Abstract: Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Saikumar Jayaraman, John S. Guzek, Yidnekachew S. Mekonnen
  • Patent number: 9859253
    Abstract: Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, John S. Guzek, Yidnekachew S. Mekonnen
  • Publication number: 20170093007
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Adel A. ELSHERBINI, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 9515031
    Abstract: In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: December 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Nevin Altunyurt, Kemal Aygun, Kevin J. Doran, Yidnekachew S. Mekonnen
  • Publication number: 20140203417
    Abstract: In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 24, 2014
    Inventors: Nevin Altunyurt, Kemal Aygun, Kevin J. Doran, Yidnekachew S. Mekonnen