Abstract: A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.

Abstract: Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

Abstract: Methods are disclosed for designing a tibial implant to minimize cortical impingement of a keel or other fixation structure when the tibial implant is implanted in the tibia bone. The design of the keel or other fixation structure on the tibial baseplate can be based on determining a common area between defined cancellous regions of at least two tibia bones. Methods are disclosed for designing a femoral component having a stem extension such that the stem can be sufficiently placed in the diaphysis of the femur when the femoral component is implanted. The method includes determining a canal axis in a femur that creates adequate engagement between a reamer and the diaphysis of the femur.

Abstract: Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.

Abstract: Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

Abstract: A circuit design verification method suitable for use with a 2.5D transceiver device potentially having hundreds of dice mounted on an interposer. An illustrative method includes: (a) retrieving a design of a circuit that includes multiple integrated circuit dice connected via an interposer, each die having at least one contact for receiving or transmitting a digital signal conveyed by an interchip connection of the interposer, said circuit including an IO cell for each such contact; (b) obtaining a timing model for components of said circuit, the timing model accounting for propagation delays of said IO cells and propagation delays of said interchip connections; (c) performing a static timing analysis of the design using the timing model to determine data required times and data arrival times at each of said components; (d) comparing the data required times with the data arrival times to detect timing violations; and (e) reporting said timing violations.

Abstract: A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.

Abstract: A method for testing operation of a device under test (DUT) includes receiving an input bit stream at an input pin, the input bit stream including multiplexed test patterns for a plurality of scan chains of the DUT. The method further includes demultiplexing the multiplexed test patterns, and providing a corresponding test pattern data to each of the plurality of scan chains. The method further includes, at each of the plurality of scan chains, scanning test results from the scan chain, to produce multiplex output test data into an output bit stream.

Abstract: Methods are disclosed for designing a tibial implant to minimize cortical impingement of a keel or other fixation structure when the tibial implant is implanted in the tibia bone. The design of the keel or other fixation structure on the tibial baseplate can be based on determining a common area between defined cancellous regions of at least two tibia bones. Methods are disclosed for designing a femoral component having a stem extension such that the stem can be sufficiently placed in the diaphysis of the femur when the femoral component is implanted. The method includes determining a canal axis in a femur that creates adequate engagement between a reamer and the diaphysis of the femur.

Abstract: Methods are disclosed for designing a tibial implant to minimize cortical impingement of a keel or other fixation structure when the tibial implant is implanted in the tibia bone. The design of the keel or other fixation structure on the tibial baseplate can be based on determining a common area between defined cancellous regions of at least two tibia bones. Methods are disclosed for designing a femoral component having a stem extension such that the stem can be sufficiently placed in the diaphysis of the femur when the femoral component is implanted. The method includes determining a canal axis in a femur that creates adequate engagement between a reamer and the diaphysis of the femur.

Abstract: A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive

Abstract: Methods are disclosed for designing a tibial implant to minimize cortical impingement of a keel or other fixation structure when the tibial implant is implanted in the tibia bone. The design of the keel or other fixation structure on the tibial baseplate can be based on determining a common area between defined cancellous regions of at least two tibia bones. Methods are disclosed for designing a femoral component having a stem extension such that the stem can be sufficiently placed in the diaphysis of the femur when the femoral component is implanted. The method includes determining a canal axis in a femur that creates adequate engagement between a reamer and the diaphysis of the femur.