Patents by Inventor Yifeng Wu
Yifeng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210408273Abstract: A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole.Type: ApplicationFiled: March 20, 2020Publication date: December 30, 2021Inventors: Yifeng WU, John Kirk GRITTERS
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Publication number: 20210391311Abstract: An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion.Type: ApplicationFiled: May 5, 2021Publication date: December 16, 2021Inventors: David Michael Rhodes, Yifeng Wu, Sung Hae Yea, Primit Parikh
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Publication number: 20210224286Abstract: This disclosure relates to a search result processing method and apparatus, and a storage medium. The method may include acquiring a search result according to a search keyword and obtaining an accurate matching score of the search result relative to the search keyword. The method may further include determining a semantic matching weight vector of the search result, a semantic representation vector of the search keyword, and a semantic representation vector of the search result. The method may further include obtaining a semantic matching score of the search result relative to the search keyword according to the semantic representation vectors and the semantic matching weight vector. The method may further include obtaining a similarity between the search result and the search keyword according to the accurate matching score and the semantic matching score.Type: ApplicationFiled: March 12, 2021Publication date: July 22, 2021Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Yifeng WU, Qiang YAN, Wenhao ZHENG, Xiaoyin CHEN, Dechuan ZHAN
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Patent number: 10897249Abstract: A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.Type: GrantFiled: March 5, 2020Date of Patent: January 19, 2021Assignee: Transphorm Technology, Inc.Inventors: Jason Cuadra, Yifeng Wu, Zhan Wang
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Patent number: 10893167Abstract: A technique includes acquiring data representing a first image produced by electronically scanning a page against a background. The first image contains a non-uniform background content due at least in part to a variation introduced by the background being non-uniform. The technique includes extracting an image of the page from the first image, wherein the extraction includes characterizing the background content of the first image; identifying candidate pixels associated with the page based at least in part on the characterized background content; and based at least in part on the identified candidate pixels and a model for a boundary of the page, determining the boundary of the page.Type: GrantFiled: April 28, 2016Date of Patent: January 12, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: David M Berfanger, Charles Jia, Yifeng Wu
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Publication number: 20200274990Abstract: A technique includes acquiring data representing a first image produced by electronically scanning a page against a background. The first image contains a non-uniform background content due at least in part to a variation introduced by the background being non-uniform. The technique includes extracting an image of the page from the first image, wherein the extraction includes characterizing the background content of the first image; identifying candidate pixels associated with the page based at least in part on the characterized background content; and based at least in part on the identified candidate pixels and a model for a boundary of the page, determining the boundary of the page.Type: ApplicationFiled: April 28, 2016Publication date: August 27, 2020Inventors: David M Berfanger, Charles Jia, Yifeng Wu
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Patent number: 10671366Abstract: A class description file describing a class associated with an application (APP) is generated based on an original file of the APP. The class description file is added to an installation package associated with the APP. Prior to execution of the APP, the installation package is downloaded. During the execution of the APP, the class description file is obtained from the installation package. The class associated with the APP is generated based on the class description file.Type: GrantFiled: June 21, 2018Date of Patent: June 2, 2020Assignee: Alibaba Group Holding LimitedInventors: Yueyang Zheng, Yifeng Wu, Haoquan Bai
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Patent number: 10630285Abstract: A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.Type: GrantFiled: November 19, 2018Date of Patent: April 21, 2020Assignee: Transphorm Technology, Inc.Inventors: Jason Cuadra, Yifeng Wu, Zhan Wang
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Patent number: 10572234Abstract: A class description file describing a class associated with an application (APP) is generated based on an original file of the APP. The class description file is added to an installation package associated with the APP. Prior to execution of the APP, the installation package is downloaded. During the execution of the APP, the class description file is obtained from the installation package. The class associated with the APP is generated based on the class description file.Type: GrantFiled: June 21, 2018Date of Patent: February 25, 2020Assignee: Alibaba Group Holding LimitedInventors: Yueyang Zheng, Yifeng Wu, Haoquan Bai
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Patent number: 10338386Abstract: A vehicle, a head-up displaying system and a projector are provided, the projector including a displaying component (1) configured to project an image, and a three-mirror optical device positioned in an optical path of an emergent light of the displaying component (1), configured to reflect the image projected by the displaying component (1) onto a front windshield (5) such that the front windshield (5) reflects the image to eyes of a driver and including: a zoom lens assembly (2) having a zoom lens (21) for zooming in/out the image projected by the displaying component (1), and a first curvature adjusting component configured to adjust a curvature of the zoom lens (21); an image quality compensation lens assembly (3) having an image quality compensation lens (31) configured to compensate for an image quality distortion caused during a change of the curvature of the zoom lens (21), and a second curvature adjusting component configured to adjust a curvature of the image quality compensation lens (31); and a frType: GrantFiled: December 25, 2015Date of Patent: July 2, 2019Assignee: BYD COMPANY LIMITEDInventors: Li Ling, Yifeng Wu, Ming Li
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Patent number: 10224427Abstract: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD).Type: GrantFiled: September 4, 2009Date of Patent: March 5, 2019Assignee: CREE, INC.Inventors: Primit Parikh, Umesh Mishra, Yifeng Wu
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Patent number: 10191290Abstract: A vehicle, a head-up displaying system and a method for adjusting a height of a projection image thereof are provided. The system includes a projector, a camera, a seat detecting module and a head-up controller. The camera is configured to detect an image having locations of the eyes of the driver and a predetermined reference point. The seat detecting module is configured to detect a position of a seat of the driver in the vehicle so as to obtain an actual horizontal distance between the eyes of the driver and the predetermined reference point. The head-up controller is configured to adjust a height of the projection image projected by the projector automatically according to the actual vertical distance. The system automatically controls the height of the projection image, and the projection image may be comfortable for the driver to view without any manual intervenes.Type: GrantFiled: December 25, 2015Date of Patent: January 29, 2019Assignee: BYD COMPANY LIMITEDInventors: Riyi Ye, Ming Li, Yifeng Wu
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Patent number: 10109713Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.Type: GrantFiled: September 30, 2016Date of Patent: October 23, 2018Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CREE INC.Inventors: Alessandro Chini, Umesh Kumar Mishra, Primit Parikh, Yifeng Wu
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Publication number: 20180300118Abstract: A class description file describing a class associated with an application (APP) is generated based on an original file of the APP. The class description file is added to an installation package associated with the APP. Prior to execution of the APP, the installation package is downloaded. During the execution of the APP, the class description file is obtained from the installation package. The class associated with the APP is generated based on the class description file.Type: ApplicationFiled: June 21, 2018Publication date: October 18, 2018Applicant: Alibaba Group Holding LimitedInventors: Yueyang ZHENG, Yifeng Wu, Haoquan Bai
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Patent number: 10063138Abstract: A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.Type: GrantFiled: February 9, 2017Date of Patent: August 28, 2018Assignee: Transphorm Inc.Inventors: Liang Zhou, Yifeng Wu
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Patent number: 9991884Abstract: A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.Type: GrantFiled: April 19, 2017Date of Patent: June 5, 2018Assignee: Transphorm Inc.Inventors: Zhan Wang, Yifeng Wu, James Honea
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Patent number: 9899998Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.Type: GrantFiled: November 12, 2014Date of Patent: February 20, 2018Assignee: Transphorm Inc.Inventors: James Honea, Yifeng Wu
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Patent number: 9866210Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.Type: GrantFiled: November 12, 2014Date of Patent: January 9, 2018Assignee: Transphorm Inc.Inventors: James Honea, Yifeng Wu
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Publication number: 20170365670Abstract: A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.Type: ApplicationFiled: September 5, 2017Publication date: December 21, 2017Inventors: Yifeng Wu, Primit Parikh, Umesh Mishra, Marcia Moore
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Publication number: 20170351093Abstract: A vehicle, a head-up displaying system and a projector are provided, the projector including a displaying component (1) configured to project an image, and a three-mirror optical device positioned in an optical path of an emergent light of the displaying component (1), configured to reflect the image projected by the displaying component (1) onto a front windshield (5) such that the front windshield (5) reflects the image to eyes of a driver and including: a zoom lens assembly (2) having a zoom lens (21) for zooming in/out the image projected by the displaying component (1), and a first curvature adjusting component configured to adjust a curvature of the zoom lens (21); an image quality compensation lens assembly (3) having an image quality compensation lens (31) configured to compensate for an image quality distortion caused during a change of the curvature of the zoom lens (21), and a second curvature adjusting component configured to adjust a curvature of the image quality compensation lens (31); and a frType: ApplicationFiled: December 25, 2015Publication date: December 7, 2017Applicant: BYD COMPANY LIMITEDInventors: Li LING, Yifeng WU, Ming LI