Abstract: An island submount used for carrying at least one light-emitting element having at least one electrical contact. The island submount includes a substrate, at least one island structure having a top surface and an inclined surface, and a conductive layer. The island structure is located on the substrate and corresponds to the electrical contact. The conductive layer is formed on the surface of the island structure and at least covers the top surface, so as to be electrically connected with the electrical contact. The island submount is capable of enhancing the light extraction efficiency of the light-emitting element, and avoids the energy loss due to re-absorption when the light emerging from below the light-emitting element is reflected back to the light-emitting element.

Abstract: A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector.

Abstract: A device of a light-emitting diode and a method for fabricating the same are provided. The LED device is made by forming a patterned epitaxial layer, a light-emitting structure, etc., on a substrate. In a subsequent process, the patterned epitaxial layer serves as a weakened structure, and can be automatically broken and a rough surface is thus formed. The weakened structure is formed with a specified height, and has pillar structures. The light-emitting structure is formed on the weakened structure. During a cooling process at room temperature, the weakened structure is automatically broken and a rough surface is thus formed.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure.

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract: A fabricating method of nitride semiconductor substrate is provided. First, a first substrate including a first base material, a nitride semiconductor template layer stacked on the first base material, and a first dielectric layer stacked on the nitride semiconductor template layer is provided. Then, the first dielectric layer and the nitride semiconductor template layer are patterned, and a second substrate including a second base material and a second dielectric layer stacked on the second base material is provided. Next, the nitride semiconductor template layer and the first dielectric layer of the first substrate are transferred onto the second dielectric layer of the second substrate through bonding and transferring processes, and then a nitride semiconductor thick film is grown from the nitride semiconductor template layer through an epitaxy process. After that, the nitride semiconductor thick film and the second substrate are separated.

Abstract: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.

Abstract: A composite material substrate having patterned structure includes a substrate, a first dielectric layer, a second dielectric layer, and a nitride semiconductor material. Herein, the first dielectric layer is stacked on the substrate, the second dielectric layer is stacked on the first dielectric layer, and the nitride semiconductor material is stacked on the second dielectric layer and is characterized by a plurality of patterns thereon.

Abstract: An initial substrate structure for forming a nitride semiconductor substrate is provided. The initial substrate structure includes a substrate, a patterned epitaxial layer, and a mask layer. The patterned epitaxial layer is located on the substrate and is formed by a plurality of pillars. The mask layer is located over the substrate and covers a part of the patterned epitaxial layer. The mask layer includes a plurality of sticks and there is a space between the sticks. The space exposes a portion of an upper surface of the patterned epitaxial layer.

Abstract: An island submount used for carrying at least one light-emitting element having at least one electrical contact. The island submount includes a substrate, at least one island structure having a top surface and an inclined surface, and a conductive layer. The island structure is located on the substrate and corresponds to the electrical contact. The conductive layer is formed on the surface of the island structure and at least covers the top surface, so as to be electrically connected with the electrical contact. The island submount is capable of enhancing the light extraction efficiency of the light-emitting element, and avoids the energy loss due to re-absorption when the light emerging from below the light-emitting element is reflected back to the light-emitting element.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: A fabricating method of nitride semiconductor substrate is provided. First, a first substrate including a first base material, a nitride semiconductor template layer stacked on the first base material, and a first dielectric layer stacked on the nitride semiconductor template layer is provided. Then, the first dielectric layer and the nitride semiconductor template layer are patterned, and a second substrate including a second base material and a second dielectric layer stacked on the second base material is provided. Next, the nitride semiconductor template layer and the first dielectric layer of the first substrate are transferred onto the second dielectric layer of the second substrate through bonding and transferring processes, and then a nitride semiconductor thick film is grown from the nitride semiconductor template layer through an epitaxy process. After that, the nitride semiconductor thick film and the second substrate are separated.

Abstract: The present invention pertains to an integrated surface-emitting optoelectronic module and the method for making the same. The yellow light procedure is performed to define a V-groove width for disposing an optical fiber on a silicon substrate. After dry etching a vertical groove, a dielectric layer is grown on the surface of the silicon substrate to protect the vertical wall, preventing the groove from getting wider due to subsequent wet etching. A 45-degree mirror surface is formed so that an optoelectronic device can be disposed on the mirror surface in the flip chip method. The optoelectronic module employs a complete silicon substrate to assemble a surface-emitting optoelectronic devices and an optical fiber by passive alignment, and therefore can be free from misalignment due to separate assembly.

Abstract: The present invention pertains to an integrated surface-emitting optoelectronic module and the method for making the same. The yellow light procedure is performed to define a V-groove width for disposing an optical fiber on a silicon substrate. After dry etching a vertical groove, a dielectric layer is grown on the surface of the silicon substrate to protect the vertical wall, preventing the groove from getting wider due to subsequent wet etching. A 45-degree mirror surface is formed so that an optoelectronic device can be disposed on the mirror surface in the flip chip method. The optoelectronic module employs a complete silicon substrate to assemble a surface-emitting optoelectronic devices and an optical fiber by passive alignment, and therefore can be free from misalignment due to separate assembly.

Abstract: A process for growing a gallium arsenide single crystal from a polycrystalline gallium arsenide by the horizontal Bridgman technique includes (a) melting the polycrystalline gallium arsenide in a quartz boat which is placed in a quartz tube, at a temperature greater than 1238 deg C. but lower than the melting point of quartz, (b) decreasing the temperature of the melt of gallium arsenide from the seed/melt interface by moving a furnace to crystallize the melt, and (c) annealing the crystallized gallium arsenide during the crystal growth process at a temperature of 1100-1220 deg C.; wherein the above steps are carried out in the absence of an As vapor pressure controlling zone which is kept at a temperature of about 617 deg C. Due to the anealing step, the thermal stress is small and the dislocation hardly occurs. A short quartz tube can be employed due to the absence of the As zone.