Patents by Inventor Yih-Yuh Doong
Yih-Yuh Doong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10679723Abstract: Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).Type: GrantFiled: December 6, 2018Date of Patent: June 9, 2020Assignee: PDF SOLUTIONS, INC.Inventors: Dong Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky, Huan Tsung Huang, Hendrik Schneider
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Patent number: 10410735Abstract: A memory-specific implementation of a test and characterization vehicle utilizes a design layout that is a modified version of the product mask. Specific routing is used to modify the product mask in order to facilitate memory cell characterization. This approach can be applied to any memory architecture with word-line and bit-line perpendicular or substantially perpendicular to each other, including but not limited to, volatile memories such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), non-volatile memory such as NAND Flash (including three-dimensional NAND Flash), NOR Flash, Phase-change RAM (PRAM), Ferroelectric RAM (FeRAM), Correlated electron RAM (CeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), XPoint memory and the like.Type: GrantFiled: February 23, 2017Date of Patent: September 10, 2019Assignee: PDF SOLUTIONS, INC.Inventors: Yih-Yuh Doong, Chao-Hsiung Lin, Sheng-Che Lin, Shihpin Kuo, Tzupin Shen, Chia-Chi Lin, Kimon Michaels
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Patent number: 10380305Abstract: A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.Type: GrantFiled: September 22, 2016Date of Patent: August 13, 2019Assignee: PDF Solutions, Inc.Inventors: Yih-Yuh Doong, Sheng-Che Lin, Chia-Chi Lin, Hans Eisenmann, Cho-Si Huang, Tzupin Shen, Christopher Hess, Kimon Michaels
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Patent number: 10096378Abstract: A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.Type: GrantFiled: February 23, 2017Date of Patent: October 9, 2018Assignee: PDF Solutions, Inc.Inventors: Yih-Yuh Doong, Chao-Hsiung Lin, Sheng-Che Lin, Shihpin Kuo, Tzupin Shen, Chia-Chi Lin, Kimon Michaels
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Patent number: 8136070Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.Type: GrantFiled: June 17, 2010Date of Patent: March 13, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kelvin Yih-Yuh Doong, Chin-Chiu Hsia
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Patent number: 8115500Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: GrantFiled: January 27, 2011Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Patent number: 8037575Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.Type: GrantFiled: September 16, 2008Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu, Tsong-Hua Ou, Min-Hong Wu, Yih-Yuh Doong, Hsiao-Shu Chao, Yi-Kan Cheng, Yao-Ching Ku, Cliff Hou
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Publication number: 20110168995Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: ApplicationFiled: January 27, 2011Publication date: July 14, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Patent number: 7880494Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: GrantFiled: March 2, 2010Date of Patent: February 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Patent number: 7849432Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.Type: GrantFiled: May 7, 2008Date of Patent: December 7, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kelvin Yih-Yuh Doong, Chin-Chiu Hsia
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Patent number: 7825678Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.Type: GrantFiled: August 22, 2008Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Tseng Chin Lo, Chien-Chang Lee, Chih-Chieh Shao
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Publication number: 20100252907Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kelvin Yih-Yuh Doong, Chin-Chiu Hsia
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Patent number: 7783999Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.Type: GrantFiled: January 18, 2008Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsong-Hua Ou, Ying-Chou Cheng, Chia-Chi Lin, Ru-Gun Liu, Chih-Ming Lai, Min-Hong Wu, Yih-Yuh Doong, Cliff Hou, Yao-Ching Ku
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Patent number: 7772868Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: GrantFiled: December 28, 2007Date of Patent: August 10, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Publication number: 20100156453Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Publication number: 20100045325Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Inventors: Yih-Yuh Doong, Tseng Chin Lo, Chien-Chang Lee, Chih-Chieh Shao
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Publication number: 20090222785Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.Type: ApplicationFiled: September 16, 2008Publication date: September 3, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chou CHENG, Chih-Ming LAI, Ru-Gun LIU, Tsong-Hua OU, Min-Hong WU, Yih-Yuh DOONG, Hsiao-Shu CHAO, Yi-Kan CHENG, Yao-Ching KU, Cliff HOU
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Publication number: 20090187866Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.Type: ApplicationFiled: January 18, 2008Publication date: July 23, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsong-Hua Ou, Ying-Chou Cheng, Chia-Chi Lin, Ru-Gun Liu, Chih-Ming Lai, Min-Hong Wu, Yih-Yuh Doong, Cliff Hou, Yao-Ching Ku
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Publication number: 20090002012Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: ApplicationFiled: December 28, 2007Publication date: January 1, 2009Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Publication number: 20080209381Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.Type: ApplicationFiled: May 7, 2008Publication date: August 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kelvin Yih-Yuh Doong, Chin-Chiu Hsia