Abstract: This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUTs) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A method for avoiding current leakage at the shallow trench isolation edge in a border-less contact process is described. Trenches are etched into a semiconductor substrate. An etch stop liner layer is deposited within the trenches and etched back to leave the etch stop liner layer only on sidewalls of the trenches. The trenches are filled with an isolation layer overlying the liner sidewalls and polished back to leave the isolation layer only within the trenches. Semiconductor device structures, including source and drain junctions, are formed in the active areas. An interlevel dielectric layer is deposited over the device structures. Border-less contact openings are etched through the ILD wherein the liner sidewalls act as an etch stop thereby preventing leakage of the source and drain junctions. The contact openings are filled with a conducting layer wherein the liner sidewalls act as a diffusion barrier to the conducting layer.

Abstract: Microanalysis of small areas on insulating substrates can be a problem because of charge and thermal buildup. One solution has been to coat the underside of the area with a layer of thermally and electrically conductive material. This becomes very difficult to do when there is no clear access to the surface in question. The present invention solves this problem by forming two cavities, on opposite sides of the area that is to be microanalyzed, that extend downwards into the substrate at an angle to its surface so that they intersect directly below the microanalysis area. The result is a cavity that is bridged by a beam having a triangular cross-section. Part of said beam is then selectively removed, resulting in a cantilever that extends out over the cavity with the microanalysis area located near its free end. Coating of the cantilever's underside is achieved by using a focused ion beam to first deposit the layer in question on the two lower sloping surfaces of the cavity.

Abstract: A test structure for detecting defects in a semiconductor wafer and a method for using such test structure are provided. The test structure includes conduction units arranged in an array and test pads connecting to the conduction units. A conduction unit includes closely spaced or intermeshed conduction paths. The test pads are divided into X and Y groups. A pair of test pads X(i), X(i+1) are set to high voltage, a pair of test pads Y(j), Y(j+1) are set to low voltage, and the other test pads are floated. The current I(i, j) flowing from test pad pairs X to Y is measured. If current I(i, j) is a local minimum, then conduction unit (i, j) has a short circuit defect.

Abstract: A test structure for detecting defects in a semiconductor wafer and a method for using such test structure are provided. The test structure includes conduction units arranged in an array and test pads connecting to the conduction units. A conduction unit includes closely spaced or intermeshed conduction paths. The test pads are divided into X and Y groups. A pair of test pads X(i), X(i+1) are set to high voltage, a pair of test pads Y(j), Y(j+1) are set to low voltage, and the other test pads are floated. The current I(i,j) flowing from test pad pairs X to Y is measured. If current I(i,j) is a local minimum, then conduction unit (i,j) has a short circuit defect.

Abstract: A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells.

Abstract: A method for forming shallow trench isolation (STI) structures on a semiconductor substrate is disclosed. First a semiconductor substrate with a first area and a second area adjacent to the first area is provided. A mask layer is formed on the substrate, and is etched to expose portions of the substrate. A first photoresist is formed to cover the second area for exposing the first area. A first implanting procedure is performed with a titled angle to form first doping areas on the substrate encroaching into portions of the substrate covered by the first photoresist. The first photoresist is removed. A second photoresist is formed on the substrate to cover the first area for exposing the second area. And a second implanting procedure is done with a titled angle to form second doping areas on the substrate encroaching into portions of the substrate covered by the second photoresist. The second photoresist is removed.

Abstract: A method of forming precisely cross-sectioned electron-transparent samples, includes removing, from a wafer, a chip containing a desired viewing site for analysis. At least one metallic mask is formed on a surface of the chip and over the viewing site using a focused ion beam microscope. Using a reactive ion etching technique, the chip is etched in a direction essentially perpendicular to the surface of the chip to form a thin viewing surface under the metallic mask. The thickness of the thin viewing surface is further reduced using a focused ion beam milling technique, to form an extremely thin electron-transparent sample.

Abstract: A method of removing thin film layers of a semiconductor component suitable for exposing a defective thin film layer for failure analysis. A focused ion beam is used instead of conventional mechanical polishing in non-selectively etching the thin film layers above a defective thin film layer in a semiconductor component. The focused ion beam has a better control over the etching thickness, so that a higher sample point success rate is obtained from a test specimen. Processing time is saved using the focused ion beam, which requires only a few minutes compared with hours needed by the conventional mechanical polishing method. The focused ion beam performs localized etching only, so that the thin film layers of other sample points in the test specimen will be unaffected. Therefore, a number of sample points can be prepared on the same test specimen at the same time.

Abstract: A method is provided for inspecting an integrated circuit chip by use of a charged-particle microscope, such as an electron or ion-beam microscope, without incurring charge effect and thermal damage to the chip. Fundamentally, the method features the forming of a coating of good electrical and heat conductive material on the back of the target portion such that the charged particles from the microscope, after passing through the target portion, will encounter the coating of good electrical and heat conductive material and thus be drawn away by the same. As a result of this, the adverse consequences of charge effect and thermal damage can be prevented. This also allows for an increase in the resolution of the resultant image of the inspected chip.