Patents by Inventor Yihwan Kim

Yihwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240381616
    Abstract: A method may include forming a first gate structure on a first region of a substrate, forming a bit line structure on the first gate structure, forming a preliminary contact plug layer including amorphous silicon on the substrate, forming a reflective layer structure on the preliminary contact plug layer, forming a contact plug layer from the preliminary contact plug layer, and forming a capacitor on the contact plug layer. The reflective layer structure may include first and second reflective layers. A refractive index of the second reflective layer may be being greater than that of the first reflective layer. Portions of the second reflective layer may have different thicknesses on first and second regions of the substrate. The forming the contact plug layer may include performing a melting laser annealing (MLA) process on the reflective layer structure to convert the amorphous silicon of the preliminary contact plug layer into polysilicon.
    Type: Application
    Filed: April 16, 2024
    Publication date: November 14, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seongkeun CHO, Suhwan HWANG, Kanguk KIM, Yihwan KIM, Jihoon KIM, Jinhyung PARK, Hyunsu SHIN, Taemin EARMME, Sungwook JUNG
  • Patent number: 12142671
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Chan Suh, Sangmoon Lee, Yihwan Kim, Woo Bin Song, Dongsuk Shin, Seung Ryul Lee
  • Publication number: 20240297215
    Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.
    Type: Application
    Filed: May 8, 2024
    Publication date: September 5, 2024
    Inventors: Sungkeun Lim, Unki Kim, Yuyeong Jo, Yihwan Kim, Jinbum Kim, Pankwi Park, Ilgyou Shin, Seunghun Lee
  • Patent number: 11996443
    Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: May 28, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkeun Lim, Unki Kim, Yuyeong Jo, Yihwan Kim, Jinbum Kim, Pankwi Park, Ilgyou Shin, Seunghun Lee
  • Publication number: 20240167162
    Abstract: A substrate processing apparatus includes a chamber providing a space for performing a semiconductor process on a semiconductor substrate, and a substrate stage configured to support the semiconductor substrate. The substrate stage includes a platen having a seating surface to support the semiconductor substrate, the platen having a resistance heater and an RF electrode adjacent to the seating surface, a shaft under the platen, the shaft having a first through hole in a central region and a plurality of second through holes in a peripheral region surrounding the central region, an RF rod spaced apart from an inner wall of the first through hole, the RF rod electrically connected to the RF electrode, and a plurality of heater rods respectively within the plurality of second through holes and electrically connected to the resistance heater.
    Type: Application
    Filed: June 29, 2023
    Publication date: May 23, 2024
    Inventors: Jihyeong LEE, Sangyeon OH, Minsung KIM, Byeongsang KIM, Yihwan KIM, Sangchul HAN
  • Publication number: 20240170308
    Abstract: An apparatus for preheating a substrate includes a preheating chamber, a cooling plate, a heater, an isolation plate, a gas supplier and a gas discharger. The preheating chamber may be configured to receive the substrate. The cooling plate may be arranged on an upper surface of the preheating chamber. The heater may be arranged between the cooling plate and the substrate to heat the substrate. The isolation plate may be arranged between the cooling plate and the substrate to form a first space between the preheating chamber and the isolation plate and a second space between the cooling plate and the isolation plate. The gas supplier may be configured to individually supply a vent gas to the first space and the second space. The gas discharge may be configured to individually supply vacuum to the first space and the second space.
    Type: Application
    Filed: June 28, 2023
    Publication date: May 23, 2024
    Inventors: Joohee KIM, Youngjae JEON, Jaehyun CHO, Yihwan KIM
  • Publication number: 20240145288
    Abstract: A substrate processing apparatus includes a chamber providing a space where a semiconductor process is performed on a semiconductor substrate, a substrate plate configured to support the semiconductor substrate, the substrate plate having a central region and a peripheral region surrounding the central region, a central embossing pattern on the central region and configured to support a central portion of the semiconductor substrate, a plurality of first embossing patterns radially arranged around the central embossing pattern on the peripheral region, each of the plurality of first embossing patterns extending radially outward from the central embossing pattern with a first length, and a plurality of second embossing patterns respectively provided between the first embossing patterns on the peripheral region, each of the plurality of second embossing patterns extending radially outward from the central embossing pattern with a second length that is less than the first length.
    Type: Application
    Filed: May 25, 2023
    Publication date: May 2, 2024
    Inventors: Youngbok LEE, Yihwan KIM, Seongkeun CHO, Sangchul HAN
  • Publication number: 20240068748
    Abstract: A wafer heating apparatus may include a heating chamber having an internal space and a heating lamp disposed in the internal space of the heating chamber. The heating lamp may be configured to heat a wafer. The heating lamp may include a plurality of lamps. Each of the plurality of lamps may have circular band shapes with open regions. At least one lamp may be disposed in at least one region among regions adjacent to the open regions of the plurality of lamps.
    Type: Application
    Filed: June 1, 2023
    Publication date: February 29, 2024
    Inventors: Joohee KIM, Youngjae JEON, Jaehyun CHO, Yihwan KIM, Sangmin LEE
  • Publication number: 20240060185
    Abstract: A substrate processing apparatus includes a chamber including a susceptor to support a substrate, a reflective housing outside the chamber, a light source in the reflective housing, the light source being configured to emit a light toward the susceptor, and a light adjuster between the light source and the susceptor, the light adjuster including a support portion supported inside the chamber and a lens coupled to the support portion, and the lens including a transmission portion configured to transmit the light and a scattering pattern portion configured to scatter the light.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 22, 2024
    Inventors: Yeontae KIM, Yihwan KIM, Hunyong PARK, Keesoo PARK, Janghwi LEE, Sungho JANG
  • Publication number: 20240019311
    Abstract: A substrate temperature measuring device includes a sensor which senses a first amount of light of a first light having a first wavelength, a second amount of light of a second light having a second wavelength, and a third amount of light of a third light having a third wavelength provided from a substrate, a first calculator to calculate a first temperature for the first wavelength, a second temperature for the second wavelength, and a third temperature of the wavelength through the first amount of light, the second amount of light and the third amount of light which are sensed, and a second calculator to calculate emissivity of the substrate and reflected energy of the substrate through the first temperature, the second temperature, and the third temperature, wherein a temperature of the substrate is calculated through the calculated emissivity of the substrate and the reflected energy of the substrate.
    Type: Application
    Filed: May 17, 2023
    Publication date: January 18, 2024
    Inventors: Yeon Tae KIM, Hun Yong PARK, Yihwan KIM, Ji Hoon KIM, Kee Soo PARK
  • Publication number: 20230315813
    Abstract: Provided is a method for classifying data in an electronic apparatus, including obtaining target data, obtaining first classification information by using a classifier set including a plurality of classifiers based on the target data, obtaining second classification information by using a neural network model based on the target data, comparing the first classification information and the second classification information, and verifying the classifier set based on a result of comparing the first classification information and the second classification information.
    Type: Application
    Filed: March 6, 2023
    Publication date: October 5, 2023
    Applicant: AiM Future Inc.
    Inventors: Yihwan KIM, Hoseok CHANG, Namsoon JUNG
  • Publication number: 20220254878
    Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Inventors: Sungkeun Lim, Unki Kim, Yuyeong Jo, Yihwan Kim, Jinbum Kim, Pankwi Park, Ilgyou Shin, Seunghun Lee
  • Patent number: 11322583
    Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkeun Lim, Unki Kim, Yuyeong Jo, Yihwan Kim, Jinbum Kim, Pankwi Park, Ilgyou Shin, Seunghun Lee
  • Publication number: 20220052187
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Inventors: Dong Chan SUH, Sangmoon LEE, Yihwan KIM, Woo Bin SONG, Dongsuk SHIN, Seung Ryul LEE
  • Patent number: 11171224
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Chan Suh, Sangmoon Lee, Yihwan Kim, Woo Bin Song, Dongsuk Shin, Seung Ryul Lee
  • Publication number: 20200373385
    Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.
    Type: Application
    Filed: March 17, 2020
    Publication date: November 26, 2020
    Inventors: Sungkeun Lim, Unki Kim, Yuyeong Jo, Yihwan Kim, Jinbum Kim, Pankwi Park, Ilgyou Shin, Seunghun Lee
  • Publication number: 20200303523
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 24, 2020
    Inventors: Dong Chan SUH, Sangmoon LEE, Yihwan KIM, Woo Bin SONG, Dongsuk SHIN, Seung Ryul LEE
  • Patent number: 10731272
    Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support including a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 4, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nyi O. Myo, Kevin Bautista, Zhiyuan Ye, Schubert S. Chu, Yihwan Kim
  • Patent number: 10692993
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Chan Suh, Sangmoon Lee, Yihwan Kim, Woo Bin Song, Dongsuk Shin, Seung Ryul Lee
  • Publication number: 20190257000
    Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support including a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 22, 2019
    Inventors: NYI O. MYO, KEVIN BAUTISTA, ZHIYUAN YE, SCHUBERT S. CHU, YIHWAN KIM