Patents by Inventor Yihwan Kim

Yihwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170314158
    Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support comprising a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 2, 2017
    Inventors: NYI O. MYO, KEVIN BAUTISTA, ZHIYUAN YE, SCHUBERT S. CHU, YIHWAN KIM
  • Patent number: 9805942
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 31, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yihwan Kim, Xuebin Li, Abhishek Dube
  • Patent number: 9721792
    Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 1, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Yihwan Kim
  • Patent number: 9704708
    Abstract: A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 11, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Yihwan Kim, Xuebin Li
  • Patent number: 9673277
    Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 6, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Adam Brand, Bingxi Sun Wood, Naomi Yoshida, Lin Dong, Shiyu Sun, Chi-Nung Ni, Yihwan Kim
  • Patent number: 9650726
    Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support comprising a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nyi O. Myo, Kevin Bautista, Zhiyuan Ye, Schubert S. Chu, Yihwan Kim
  • Publication number: 20170098547
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventors: Yihwan KIM, Xuebin LI, Abhishek DUBE
  • Patent number: 9530661
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: December 27, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yihwan Kim, Xuebin Li, Abhishek Dube
  • Patent number: 9460918
    Abstract: Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, and is formed without the addition of carbon. A phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater increases the tensile strain of the deposited layer, and thus, improves channel mobility. Since the epitaxial layer is substantially free of carbon, the epitaxial layer does not suffer from film formation and quality issues commonly associated with carbon-containing epitaxial layers.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 4, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Ye, Xuebin Li, Saurabh Chopra, Yihwan Kim
  • Publication number: 20160111495
    Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 21, 2016
    Inventors: ADAM BRAND, BINGXI SUN WOOD, NAOMI YOSHIDA, LIN DONG, SHIYU SUN, CHI-NUNG NI, YIHWAN KIM
  • Publication number: 20160042963
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.
    Type: Application
    Filed: July 14, 2015
    Publication date: February 11, 2016
    Inventors: Yihwan KIM, Xuebin LI, Abhishek DUBE
  • Publication number: 20160013274
    Abstract: A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 14, 2016
    Inventors: Abhishek DUBE, Yihwan KIM, Xuebin LI
  • Publication number: 20150368796
    Abstract: Embodiments described herein generally relate to apparatus for forming silicon epitaxial layers on semiconductor devices. Deposition gases and etching gases may be provided sequentially or simultaneously to improve epitaxial layer deposition characteristics. A gas distribution assembly may be coupled to a deposition gas source and an etching gas source. Deposition gas and etching gas may remain separated until the gases are provided to a processing volume in a processing chamber. Outlets of the gas distribution assembly may be configured to provide the deposition gas and etching gas into the processing volume with varying characteristics. In one embodiment, outlets of the gas distribution assembly which deliver etching gas to the processing volume may be angled upward relative to a surface of a substrate.
    Type: Application
    Filed: June 19, 2015
    Publication date: December 24, 2015
    Inventors: Xuebin LI, Kevin JOSEPH BAUTISTA, Avinash SHERVEGAR, Yihwan KIM, Nyi O. MYO, Abhishek DUBE
  • Patent number: 9200367
    Abstract: Methods and apparatus for gas delivery are disclosed herein. In some embodiments, a gas delivery system includes an ampoule for storing a precursor in solid or liquid form, a first conduit coupled to the ampoule and having a first end coupled to a first gas source to draw a vapor of the precursor from the ampoule into the first conduit, a second conduit coupled to the first conduit at a first junction located downstream of the ampoule and having a first end coupled to a second gas source and a second end coupled to a process chamber, and a heat source configured to heat the ampoule and at least a first portion of the first conduit from the ampoule to the second conduit and to heat only a second portion of the second conduit, wherein the second portion of the second conduit includes the first junction.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: December 1, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Ye, Yihwan Kim
  • Publication number: 20150221730
    Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Inventors: Zhiyuan YE, Xuebin LI, Saurabh CHOPRA, Yihwan KIM
  • Patent number: 9064960
    Abstract: Methods of selectively and epitaxially forming a silicon-containing material on a substrate surface contained within a process chamber are provided. In one or more embodiments, the pressure in the process chamber is reduced during deposition of material on the substrate and increased during etching of material from the substrate. According to an embodiment, process gases are flowed into the chamber through first zone and a second zone to provide a ratio of the amount of gas flowed to the first zone and the amount of gas flowed to the second zone. In one or more embodiments, the first zone is an inner radial zone and the second zone is an outer radial zone, and ratio of inner zone gas flow to outer zone gas flow is less during deposition than during etching. According to one or more embodiments, the selective epitaxial process includes repeating a cycle of a deposition and then an etching process, and an optional purge until the desired thickness of an epitaxial layer is grown.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: June 23, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Andrew Lam, Yihwan Kim
  • Patent number: 9058988
    Abstract: Methods of depositing layers having reduced interfacial contamination are disclosed herein. The inventive methods may advantageously reduce contamination at the interface between deposited layers, for example, between a deposited layer and an underlying substrate or film. In some embodiments, a method of depositing a layer may include annealing a silicon-containing layer having a first layer disposed thereon in a reducing atmosphere; removing the first layer using an etching process to expose the silicon-containing layer after annealing; and depositing a second layer on the exposed silicon-containing layer.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: June 16, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jean R. Vatus, Jinsong Tang, Yihwan Kim, Satheesh Kuppurao, Errol Sanchez
  • Patent number: 9012328
    Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Xuebin Li, Saurabh Chopra, Yihwan Kim
  • Patent number: 8999821
    Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Adam Brand, Bingxi Wood, Errol Sanchez, Yihwan Kim, Yi-Chiau Huang, John Boland
  • Publication number: 20150079803
    Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 19, 2015
    Inventors: Yi-Chiau HUANG, Yihwan KIM