Abstract: A method of increasing crude oil production by CO2 storage in an aquifer and dumpflooding includes the following steps. Wells are drilled in an aquifer in an oil-bearing basin for large-scale CO2 storage. A low-production and low-efficiency well in an oil-bearing stratum away from the CO2 storage injection well is selected as an artesian injection well. Formation water in the aquifer with increasing pressure is controlled and guided into the oil-bearing stratum to realize oil displacement by dumpflooding in the oil-bearing stratum.

Abstract: Systems and methods are directed to generating behavioral predictions in reaction to autonomous vehicle movement. In one example, a computer-implemented method includes obtaining, by a computing system, local scene data associated with an environment external to an autonomous vehicle, the local scene data including actor data for an actor in the environment external to the autonomous vehicle. The method includes extracting, by the computing system and from the local scene data, one or more actor prediction parameters for the actor using a machine-learned parameter extraction model. The method includes determining, by the computing system, a candidate motion plan for the autonomous vehicle. The method includes generating, by the computing system and using a machine-learned prediction model, a reactive prediction for the actor based at least in part on the one or more actor prediction parameters and the candidate motion plan.

Abstract: Systems and methods are directed to generating behavioral predictions in reaction to autonomous vehicle movement. In one example, a computer-implemented method includes obtaining, by a computing system, local scene data associated with an environment external to an autonomous vehicle, the local scene data including actor data for an actor in the environment external to the autonomous vehicle. The method includes extracting, by the computing system and from the local scene data, one or more actor prediction parameters for the actor using a machine-learned parameter extraction model. The method includes determining, by the computing system, a candidate motion plan for the autonomous vehicle. The method includes generating, by the computing system and using a machine-learned prediction model, a reactive prediction for the actor based at least in part on the one or more actor prediction parameters and the candidate motion plan.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer is grown. The epitaxial layer covers the first trenches and the second trenches but not the third trenches. First and second recesses on a top surface of the epitaxial layer are formed. First and second openings aligned with the first and the second recesses and a third openings aligned with the third trenches are formed in a photoresist layer. A corresponding first offset between a top center and a bottom center of each first recess is measured. An offset value of the top center from the bottom center of said each first recess is determined. A corresponding second offset between a top center of each second recess and a center of corresponding second opening is determined. A corresponding third offset between a center of each third trench and a center of corresponding third opening is measured.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: A cylindrical reticle system is provided for performing a unidirectional scan-exposure. The cylindrical reticle system includes a base and a center shaft fixed a one side of the base. The cylindrical reticle system also includes a first bearing fixed at the end of the center shaft near to the base and a second bearing fixed at the other end of the center shaft far from the base. Further, the cylindrical reticle system includes a cylindrical reticle having an imaging region and two non-imaging regions at both end of the imaging region.

Abstract: An exposure apparatus is provided for performing an unidirectional scan-exposure. The exposure apparatus includes a base and a wafer stage group having a plurality of wafer stages on the base for holding wafers and successively moving from a first position to a second position of the base cyclically. The exposure apparatus also includes an alignment detection unit above the first position for detecting wafer stage fiducials at the first position and alignment marks on a wafer on the wafer stage to align the wafer. Further, the exposure apparatus includes a reticle stage on the second position for loading a cylindrical reticle and causing the cylindrical reticle to rotate around the center axis of the reticle stage and an optical projection unit between the reticle stage and the base for projecting light passing through the cylindrical reticle onto exposure regions on a wafer on the wafer stage.

Abstract: This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: An exposure method and an exposure device are provided. An exemplary exposure device includes a stage, a first clamp holder, a second clamp holder, an optical projection unit, a first alignment detection unit, and/or a second alignment detection unit. The stage includes a first region and a second region. The first clamp holder is located in the first region and adapted for holding a first substrate, and the second clamp holder is located in the second region and adapted for holding a second substrate. The optical projection unit is located above the stage and adapted for exposure of the first substrate or the second substrate. The first alignment detection unit is adapted for detecting alignment marks of the first substrate. The second alignment detection unit is adapted for detecting alignment marks of the second substrate. The exposure device can accurately position the stage and improve production yield.

Abstract: The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.

Abstract: Embodiments relate to a method, optical module and auto-focusing system for wafer edge exposure. The optical module comprises a light source emitting light of a wavelength to expose a photoresist, an exposing optics and a mask with an aperture between the light source and the exposing optics. The light emitted from the light source passes through the mask and then reaches the exposing optics to image the aperture on the wafer edge covered with the photoresist to form a focused light spot. The positions of the light source, the mask and the exposing optics, and the size of the aperture are configured such that the optical axis of the incident light is perpendicular to the wafer surface, and the light spot completely covers the wafer edge in the radial direction of the wafer.