Abstract: A deep-sea sound source localization method, a computer device and a storage medium. The method includes: deploying at least two underwater gliders in a designated sea area, so as to respectively record a broadband signal which is emitted by a broadband sound source (1); obtaining a waveform envelope of the signal, and then calculating a waveform envelope of a simulated signal (2); performing cross-correlation analysis on the two waveform envelopes (3); and determining an estimated value of a distance from the sound source, and finally obtaining an estimated position of the sound source by means of a geometrical relationship (3). By means of the method, deployment of a large-depth vertical receiving array is not required. The system has low complexity, and is easy to deploy and operate, which can be applied to a relatively large area.

Abstract: Systems and methods are directed to generating behavioral predictions in reaction to autonomous vehicle movement. In one example, a computer-implemented method includes obtaining, by a computing system, local scene data associated with an environment external to an autonomous vehicle, the local scene data including actor data for an actor in the environment external to the autonomous vehicle. The method includes extracting, by the computing system and from the local scene data, one or more actor prediction parameters for the actor using a machine-learned parameter extraction model. The method includes determining, by the computing system, a candidate motion plan for the autonomous vehicle. The method includes generating, by the computing system and using a machine-learned prediction model, a reactive prediction for the actor based at least in part on the one or more actor prediction parameters and the candidate motion plan.

Abstract: An aspect of the disclosed technology is a system and process that are able to answer a document query as text and also provide the location in an image where the answer text is detected. In one aspect of the disclosed technology, a machine learning model combines vision and language features for joint learning.

Abstract: Systems and methods for predicting interactions between objects and predicting a trajectory of an object are presented herein. A system can obtain object data associated with a first object and a second object. The object data can have position data and velocity data for the first object and the second object. Additionally, the system can process the obtained object data to generate a hybrid graph using a graph generator. The hybrid graph can have a first node indicative of the first object and a second node indicative of the second object. Moreover, the system can process, using an interaction prediction model, the generated hybrid graph to predict an interaction type between the first node and the second node. Furthermore, the system can process, using a graph neural network model, the predicted interaction type between the first node and the second node to predict a trajectory of the first object.

Abstract: Systems and methods for predicting interactions between objects and predicting a trajectory of an object are presented herein. A system can obtain object data associated with a first object and a second object. The object data can have position data and velocity data for the first object and the second object. Additionally, the system can process the obtained object data to generate a hybrid graph using a graph generator. The hybrid graph can have a first node indicative of the first object and a second node indicative of the second object. Moreover, the system can process, using an interaction prediction model, the generated hybrid graph to predict an interaction type between the first node and the second node. Furthermore, the system can process, using a graph neural network model, the predicted interaction type between the first node and the second node to predict a trajectory of the first object.

Abstract: Systems and methods are directed to generating behavioral predictions in reaction to autonomous vehicle movement. In one example, a computer-implemented method includes obtaining, by a computing system, local scene data associated with an environment external to an autonomous vehicle, the local scene data including actor data for an actor in the environment external to the autonomous vehicle. The method includes extracting, by the computing system and from the local scene data, one or more actor prediction parameters for the actor using a machine-learned parameter extraction model. The method includes determining, by the computing system, a candidate motion plan for the autonomous vehicle. The method includes generating, by the computing system and using a machine-learned prediction model, a reactive prediction for the actor based at least in part on the one or more actor prediction parameters and the candidate motion plan.

Abstract: Systems and methods are directed to generating behavioral predictions in reaction to autonomous vehicle movement. In one example, a computer-implemented method includes obtaining, by a computing system, local scene data associated with an environment external to an autonomous vehicle, the local scene data including actor data for an actor in the environment external to the autonomous vehicle. The method includes extracting, by the computing system and from the local scene data, one or more actor prediction parameters for the actor using a machine-learned parameter extraction model. The method includes determining, by the computing system, a candidate motion plan for the autonomous vehicle. The method includes generating, by the computing system and using a machine-learned prediction model, a reactive prediction for the actor based at least in part on the one or more actor prediction parameters and the candidate motion plan.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer is grown. The epitaxial layer covers the first trenches and the second trenches but not the third trenches. First and second recesses on a top surface of the epitaxial layer are formed. First and second openings aligned with the first and the second recesses and a third openings aligned with the third trenches are formed in a photoresist layer. A corresponding first offset between a top center and a bottom center of each first recess is measured. An offset value of the top center from the bottom center of said each first recess is determined. A corresponding second offset between a top center of each second recess and a center of corresponding second opening is determined. A corresponding third offset between a center of each third trench and a center of corresponding third opening is measured.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: A cylindrical reticle system is provided for performing a unidirectional scan-exposure. The cylindrical reticle system includes a base and a center shaft fixed a one side of the base. The cylindrical reticle system also includes a first bearing fixed at the end of the center shaft near to the base and a second bearing fixed at the other end of the center shaft far from the base. Further, the cylindrical reticle system includes a cylindrical reticle having an imaging region and two non-imaging regions at both end of the imaging region.

Abstract: An exposure apparatus is provided for performing an unidirectional scan-exposure. The exposure apparatus includes a base and a wafer stage group having a plurality of wafer stages on the base for holding wafers and successively moving from a first position to a second position of the base cyclically. The exposure apparatus also includes an alignment detection unit above the first position for detecting wafer stage fiducials at the first position and alignment marks on a wafer on the wafer stage to align the wafer. Further, the exposure apparatus includes a reticle stage on the second position for loading a cylindrical reticle and causing the cylindrical reticle to rotate around the center axis of the reticle stage and an optical projection unit between the reticle stage and the base for projecting light passing through the cylindrical reticle onto exposure regions on a wafer on the wafer stage.

Abstract: This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.