Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract: An exposure method and an exposure device are provided. An exemplary exposure device includes a stage, a first clamp holder, a second clamp holder, an optical projection unit, a first alignment detection unit, and/or a second alignment detection unit. The stage includes a first region and a second region. The first clamp holder is located in the first region and adapted for holding a first substrate, and the second clamp holder is located in the second region and adapted for holding a second substrate. The optical projection unit is located above the stage and adapted for exposure of the first substrate or the second substrate. The first alignment detection unit is adapted for detecting alignment marks of the first substrate. The second alignment detection unit is adapted for detecting alignment marks of the second substrate. The exposure device can accurately position the stage and improve production yield.

Abstract: The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.

Abstract: Embodiments relate to a method, optical module and auto-focusing system for wafer edge exposure. The optical module comprises a light source emitting light of a wavelength to expose a photoresist, an exposing optics and a mask with an aperture between the light source and the exposing optics. The light emitted from the light source passes through the mask and then reaches the exposing optics to image the aperture on the wafer edge covered with the photoresist to form a focused light spot. The positions of the light source, the mask and the exposing optics, and the size of the aperture are configured such that the optical axis of the incident light is perpendicular to the wafer surface, and the light spot completely covers the wafer edge in the radial direction of the wafer.

Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer.

Abstract: A photolithographic apparatus for use with a photo-resist comprises a first component that generates a first chemical substance and produces a chemical amplification action and a second component that generates a second chemical substance. The photolithographic apparatus comprises a first exposure subsystem for selectively illuminating a surface of the photo-resist using a light of a first wavelength band such that the first component generates the first chemical substance and a second exposure subsystem for uniformly illuminating the surface using a light of a second wavelength band such that the second component generates the second chemical substance. The second chemical substance reacts with the first chemical substance to reduce the mass concentration of the first chemical substance in the photo-resist and improves the contrast of a latent image of the first chemical substance formed in the photo-resist.

Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer.

Abstract: A photo-resist and a method for performing photolithography using the photo-resist are described. The photo-resist comprises a matrix resin, a first component and a second component. The first component is configured to produce a chemical amplification action and generates a first chemical substance when exposed to a light of a first wavelength band. The first chemical substance will react with the matrix resin to form a latent image. The second component is configured to generate a second chemical substance when exposed to a light of a second wavelength band. The second chemical substance reacts with the first chemical substance to reduce a mass concentration of the first chemical substance.

Abstract: A photolithographic apparatus for use with a photo-resist comprises a first component that generates a first chemical substance and produces a chemical amplification action and a second component that generates a second chemical substance. The photolithographic apparatus comprises a first exposure subsystem for selectively illuminating a surface of the photo-resist using a light of a first wavelength band such that the first component generates the first chemical substance and a second exposure subsystem for uniformly illuminating the surface using a light of a second wavelength band such that the second component generates the second chemical substance. The second chemical substance reacts with the first chemical substance to reduce the mass concentration of the first chemical substance in the photo-resist and improves the contrast of a latent image of the first chemical substance formed in the photo-resist.

Abstract: Embodiments relate to a method, optical module and auto-focusing system for wafer edge exposure. The optical module comprises a light source emitting light of a wavelength to expose a photoresist, an exposing optics and a mask with an aperture between the light source and the exposing optics. The light emitted from the light source passes through the mask and then reaches the exposing optics to image the aperture on the wafer edge covered with the photoresist to form a focused light spot. The positions of the light source, the mask and the exposing optics, and the size of the aperture are configured such that the optical axis of the incident light is perpendicular to the wafer surface, and the light spot completely covers the wafer edge in the radial direction of the wafer.

Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

Abstract: A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature.

Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

Abstract: Semiconductor devices and fabrication methods are provided, in which gate defects associated with photoresist stress after plasma trim/etch are substantially reduced. The method comprises forming a gate dielectric layer above a semiconductor body substrate; coating the gate dielectric layer with a photoresist coating; exposing and developing the photoresist coating; performing a resist annealing; and trimming and etching the photoresist coating.

Abstract: Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.

Abstract: A method for determining photoresist thickness is disclosed that can be used in a semiconductor fabrication process. A layer of material is formed that has one or more common characteristic relative to the material in the layer that is to be patterned in the semiconductor fabrication process. A layer of photoresist is then formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of different points. The layer of photoresist is exposed, developed and etched. The remaining structures are then analyzed to determine photoresist thickness to be used in the semiconductor fabrication process. The determined photoresist thickness is then used in the semiconductor fabrication process to form structures on a semiconductor wafer.

Abstract: The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is performed so as to form trenches within the semiconductor substrate. An anti-reflective film is deposited such that it extends within the trench. A dielectric film is deposited over the anti-reflective film such that it fills the trench. A heating process step is then performed to anneal the substrate, rounding the corners of the trench. A chemical mechanical polishing process is performed to remove those portions of the anti-reflective film and the dielectric film that overlie the hard mask. The hard mask is then removed, producing a shallow trench isolation structure that prevents lifting and notching in subsequent fabrication steps.

Abstract: A method for generating a photoresist structure is disclosed in which a layer of photoresist is deposited over a semiconductor substrate. In a first exposure, the layer of photoresist is exposed to deep ultraviolet light. A second exposure is then performed using a different wavelength of light to pattern the layer of photoresist. The photoresist is then developed so as to form a photoresist structure having reduced thickness and rounded corners. This gives a photoresist structure having a reduced shadow area. An angled ion implant can then be performed using the photoresist structure as a mask.

Abstract: A method for forming a photoresist structure that does not have swelling defects. A layer of low activation energy deep ultraviolet photoresist is disposed over a layer that is to be patterned. A layer of high activation energy deep ultraviolet photoresist is then deposited such that the layer of high activation energy photoresist directly overlies the layer of low activation energy photoresist. The two photoresist layers are then processed by performing exposure, post-exposure bake, and development steps to form a photoresist structure. An etch step is then performed so as to form a patterned layer that does not have swelling defects.

Abstract: A method for generating a swing curve and a photoresist feature formed using the swing curve. A layer of photoresist is formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of points. The semiconductor wafer is then exposed and developed to form a photoresist structure that includes features. For each of the points at which thickness was determined, the size of a corresponding feature is determined. A curve is then determined that correlates the thickness measurements and the size measurements. The resulting swing curve is then used to determine a thickness for photoresist deposition and a photoresist layer is deposited, exposed, and developed to obtain a photoresist feature having the desired size.